luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
Code Issues Packages Projects Releases Wiki Activity

Move DRC/LVS/PEX tools to tech file.

Browse Source
This commit is contained in:
Matt Guthaus
2019-11-29 12:01:33 -08:00
parent abd8b0a23a
commit d511f648c6
13 changed files with 86 additions and 67 deletions
Download Patch File Download Diff File Expand all files Collapse all files
technology/freepdk45/config.py
+7
View File
@@ -0,0 +1,7 @@
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]
drc_name = "calibre"
lvs_name = "calibre"
pex_name = "calibre"
technology/freepdk45/tech/tech.py
+11
View File
@@ -336,3 +336,14 @@ parameter["bitcell_drain_cap"] = 0.1 #In Femto-Farad, approximation of dr
##END Spice Simulation Parameters
###################################################
###################################################
##BEGIN Technology Tool Preferences
###################################################
drc_name = "calibre"
lvs_name = "calibre"
pex_name = "calibre"
###################################################
##END Technology Tool Preferences
###################################################
technology/scn3me_subm/__init__.py
+1 -5
View File
@@ -35,9 +35,5 @@ except:
DRCLVS_HOME=OPENRAM_TECH+"/scn3me_subm/tech"
os.environ["DRCLVS_HOME"] = DRCLVS_HOME
# try:
# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
# except:
OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY)
os.environ["SPICE_MODEL_DIR"] = "{0}/models".format(os.path.dirname(__file__))
technology/scn3me_subm/tech/tech.py
+12
View File
@@ -277,3 +277,15 @@ parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of dr
###################################################
##END Spice Simulation Parameters
###################################################
###################################################
##BEGIN Technology Tool Preferences
###################################################
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"
###################################################
##END Technology Tool Preferences
###################################################
technology/scn4m_subm/__init__.py
+1 -5
View File
@@ -35,9 +35,5 @@ except:
DRCLVS_HOME=OPENRAM_TECH+"/scn4m_subm/tech"
os.environ["DRCLVS_HOME"] = DRCLVS_HOME
# try:
# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
# except:
OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY)
os.environ["SPICE_MODEL_DIR"] = "{0}/models".format(os.path.dirname(__file__))
technology/scn4m_subm/config.py
+7
View File
@@ -0,0 +1,7 @@
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"
technology/scn4m_subm/tech/tech.py
+12
View File
@@ -301,3 +301,15 @@ parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of dr
###################################################
##END Spice Simulation Parameters
###################################################
###################################################
##BEGIN Technology Tool Preferences
###################################################
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"
###################################################
##END Technology Tool Preferences
###################################################