From d511f648c65e24004a2daf90f6c8ef92b5cfe159 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 29 Nov 2019 12:01:33 -0800 Subject: [PATCH] Move DRC/LVS/PEX tools to tech file. --- compiler/globals.py | 18 +++++++++++--- compiler/options.py | 6 +++-- compiler/tests/configs/config.py | 14 ----------- compiler/tests/configs/config_back_end.py | 12 --------- compiler/tests/configs/config_front_end.py | 13 ---------- compiler/verify/__init__.py | 29 +++++++++++++--------- technology/freepdk45/config.py | 7 ++++++ technology/freepdk45/tech/tech.py | 11 ++++++++ technology/scn3me_subm/__init__.py | 6 +---- technology/scn3me_subm/tech/tech.py | 12 +++++++++ technology/scn4m_subm/__init__.py | 6 +---- technology/scn4m_subm/config.py | 7 ++++++ technology/scn4m_subm/tech/tech.py | 12 +++++++++ 13 files changed, 86 insertions(+), 67 deletions(-) create mode 100644 technology/freepdk45/config.py create mode 100644 technology/scn4m_subm/config.py diff --git a/compiler/globals.py b/compiler/globals.py index 464bafd0..3a8153bd 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -448,14 +448,24 @@ def init_paths(): def set_default_corner(): """ Set the default corner. """ - + + import tech # Set some default options now based on the technology... if (OPTS.process_corners == ""): - OPTS.process_corners = tech.spice["fet_models"].keys() + if OPTS.nominal_corner_only: + OPTS.process_corners = ["TT"] + else: + OPTS.process_corners = tech.spice["fet_models"].keys() if (OPTS.supply_voltages == ""): - OPTS.supply_voltages = tech.spice["supply_voltages"] + if OPTS.nominal_corner_only: + OPTS.supply_voltages = [tech.spice["supply_voltages"][1]] + else: + OPTS.supply_voltages = tech.spice["supply_voltages"] if (OPTS.temperatures == ""): - OPTS.temperatures = tech.spice["temperatures"] + if OPTS.nominal_corner_only: + OPTS.temperatures = [tech.spice["temperatures"][1]] + else: + OPTS.temperatures = tech.spice["temperatures"] def import_tech(): diff --git a/compiler/options.py b/compiler/options.py index 56bd1757..444730c1 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -34,6 +34,7 @@ class options(optparse.Values): write_size = None # These will get initialized by the user or the tech file + nominal_corner_only = True supply_voltages = "" temperatures = "" process_corners = "" @@ -85,6 +86,8 @@ class options(optparse.Values): check_lvsdrc = False # This determines whether LVS and DRC is checked for every submodule. inline_lvsdrc = False + # Treat the bitcell as a black box (no DRC, LVS, or extraction) + blackbox_bitcell = False # Remove noncritical memory cells for characterization speed-up trim_netlist = False # Run with extracted parasitics @@ -110,8 +113,7 @@ class options(optparse.Values): # Should we print out the banner at startup print_banner = True - # Use detailed LEF blockages - detailed_blockages = True + # Define the output file paths output_path = "." # Define the output file base name diff --git a/compiler/tests/configs/config.py b/compiler/tests/configs/config.py index 52344e41..b876c07d 100644 --- a/compiler/tests/configs/config.py +++ b/compiler/tests/configs/config.py @@ -11,20 +11,6 @@ num_words = 16 tech_name = OPTS.tech_name -process_corners = ["TT"] -supply_voltages = [5.0] -temperatures = [25] - route_supplies = True check_lvsdrc = True -if tech_name.startswith("scn"): - drc_name = "magic" - lvs_name = "netgen" - pex_name = "magic" -else: - supply_voltages = [1.0] - drc_name = "calibre" - lvs_name = "calibre" - pex_name = "calibre" - diff --git a/compiler/tests/configs/config_back_end.py b/compiler/tests/configs/config_back_end.py index 2a7223f5..8f195e7a 100644 --- a/compiler/tests/configs/config_back_end.py +++ b/compiler/tests/configs/config_back_end.py @@ -10,22 +10,10 @@ word_size = 1 num_words = 16 tech_name = OPTS.tech_name -process_corners = ["TT"] -supply_voltages = [5.0] -temperatures = [25] route_supplies = True check_lvsdrc = True inline_lvsdrc = True analytical_delay = False -if tech_name.startswith("scn"): - drc_name = "magic" - lvs_name = "netgen" - pex_name = "magic" -else: - supply_voltages = [1.0] - drc_name = "calibre" - lvs_name = "calibre" - pex_name = "calibre" diff --git a/compiler/tests/configs/config_front_end.py b/compiler/tests/configs/config_front_end.py index 0a9bda4e..1ea88cd4 100644 --- a/compiler/tests/configs/config_front_end.py +++ b/compiler/tests/configs/config_front_end.py @@ -10,18 +10,5 @@ word_size = 1 num_words = 16 tech_name = OPTS.tech_name -process_corners = ["TT"] -supply_voltages = [5.0] -temperatures = [25] - -if tech_name.startswith("scn"): - drc_name = "magic" - lvs_name = "netgen" - pex_name = "magic" -else: - supply_voltages = [1.0] - drc_name = "calibre" - lvs_name = "calibre" - pex_name = "calibre" diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index 042fecff..59df42db 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -17,7 +17,12 @@ If not, OpenRAM will continue as if nothing happened! import os import debug -from globals import OPTS,find_exe,get_tool +from globals import OPTS +from globals import find_exe +from globals import get_tool +from tech import drc_name +from tech import lvs_name +from tech import pex_name import sys debug.info(1,"Initializing verify...") @@ -29,29 +34,29 @@ if not OPTS.check_lvsdrc: OPTS.pex_exe = None else: debug.info(1, "Finding DRC/LVS/PEX tools.") - OPTS.drc_exe = get_tool("DRC", ["calibre","assura","magic"], OPTS.drc_name) - OPTS.lvs_exe = get_tool("LVS", ["calibre","assura","netgen"], OPTS.lvs_name) - OPTS.pex_exe = get_tool("PEX", ["calibre","magic"], OPTS.pex_name) + OPTS.drc_exe = get_tool("DRC", ["calibre","assura","magic"], drc_name) + OPTS.lvs_exe = get_tool("LVS", ["calibre","assura","netgen"], lvs_name) + OPTS.pex_exe = get_tool("PEX", ["calibre","magic"], pex_name) if OPTS.drc_exe == None: - from .none import run_drc,print_drc_stats + from .none import run_drc, print_drc_stats elif "calibre"==OPTS.drc_exe[0]: - from .calibre import run_drc,print_drc_stats + from .calibre import run_drc, print_drc_stats elif "assura"==OPTS.drc_exe[0]: - from .assura import run_drc,print_drc_stats + from .assura import run_drc, print_drc_stats elif "magic"==OPTS.drc_exe[0]: - from .magic import run_drc,print_drc_stats + from .magic import run_drc, print_drc_stats else: debug.warning("Did not find a supported DRC tool.") if OPTS.lvs_exe == None: - from .none import run_lvs,print_lvs_stats + from .none import run_lvs, print_lvs_stats elif "calibre"==OPTS.lvs_exe[0]: - from .calibre import run_lvs,print_lvs_stats + from .calibre import run_lvs, print_lvs_stats elif "assura"==OPTS.lvs_exe[0]: - from .assura import run_lvs,print_lvs_stats + from .assura import run_lvs, print_lvs_stats elif "netgen"==OPTS.lvs_exe[0]: - from .magic import run_lvs,print_lvs_stats + from .magic import run_lvs, print_lvs_stats else: debug.warning("Did not find a supported LVS tool.") diff --git a/technology/freepdk45/config.py b/technology/freepdk45/config.py new file mode 100644 index 00000000..6058bb64 --- /dev/null +++ b/technology/freepdk45/config.py @@ -0,0 +1,7 @@ +process_corners = ["TT"] +supply_voltages = [1.0] +temperatures = [25] + +drc_name = "calibre" +lvs_name = "calibre" +pex_name = "calibre" diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index ff55bcc7..14db2ea4 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -336,3 +336,14 @@ parameter["bitcell_drain_cap"] = 0.1 #In Femto-Farad, approximation of dr ##END Spice Simulation Parameters ################################################### +################################################### +##BEGIN Technology Tool Preferences +################################################### + +drc_name = "calibre" +lvs_name = "calibre" +pex_name = "calibre" + +################################################### +##END Technology Tool Preferences +################################################### diff --git a/technology/scn3me_subm/__init__.py b/technology/scn3me_subm/__init__.py index 87b26056..6b08d0b9 100644 --- a/technology/scn3me_subm/__init__.py +++ b/technology/scn3me_subm/__init__.py @@ -35,9 +35,5 @@ except: DRCLVS_HOME=OPENRAM_TECH+"/scn3me_subm/tech" os.environ["DRCLVS_HOME"] = DRCLVS_HOME -# try: -# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR")) -# except: -OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) -os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY) +os.environ["SPICE_MODEL_DIR"] = "{0}/models".format(os.path.dirname(__file__)) diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index cc405c21..6fc68686 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -277,3 +277,15 @@ parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of dr ################################################### ##END Spice Simulation Parameters ################################################### + +################################################### +##BEGIN Technology Tool Preferences +################################################### + +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" + +################################################### +##END Technology Tool Preferences +################################################### diff --git a/technology/scn4m_subm/__init__.py b/technology/scn4m_subm/__init__.py index c7a863f0..5fbd8c08 100644 --- a/technology/scn4m_subm/__init__.py +++ b/technology/scn4m_subm/__init__.py @@ -35,9 +35,5 @@ except: DRCLVS_HOME=OPENRAM_TECH+"/scn4m_subm/tech" os.environ["DRCLVS_HOME"] = DRCLVS_HOME -# try: -# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR")) -# except: -OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) -os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY) +os.environ["SPICE_MODEL_DIR"] = "{0}/models".format(os.path.dirname(__file__)) diff --git a/technology/scn4m_subm/config.py b/technology/scn4m_subm/config.py new file mode 100644 index 00000000..ed604578 --- /dev/null +++ b/technology/scn4m_subm/config.py @@ -0,0 +1,7 @@ +process_corners = ["TT"] +supply_voltages = [5.0] +temperatures = [25] + +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 8d466023..be3ab83c 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -301,3 +301,15 @@ parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of dr ################################################### ##END Spice Simulation Parameters ################################################### + +################################################### +##BEGIN Technology Tool Preferences +################################################### + +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" + +################################################### +##END Technology Tool Preferences +###################################################