luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity

Move DRC/LVS/PEX tools to tech file.

Browse Source
This commit is contained in:
Matt Guthaus
2019-11-29 12:01:33 -08:00
parent abd8b0a23a
commit d511f648c6
13 changed files with 86 additions and 67 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/tests/configs/config.py
-14
View File
@@ -11,20 +11,6 @@ num_words = 16
tech_name = OPTS.tech_name
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
route_supplies = True
check_lvsdrc = True
if tech_name.startswith("scn"):
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"
else:
supply_voltages = [1.0]
drc_name = "calibre"
lvs_name = "calibre"
pex_name = "calibre"
compiler/tests/configs/config_back_end.py
-12
View File
@@ -10,22 +10,10 @@ word_size = 1
num_words = 16
tech_name = OPTS.tech_name
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
route_supplies = True
check_lvsdrc = True
inline_lvsdrc = True
analytical_delay = False
if tech_name.startswith("scn"):
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"
else:
supply_voltages = [1.0]
drc_name = "calibre"
lvs_name = "calibre"
pex_name = "calibre"
compiler/tests/configs/config_front_end.py
-13
View File
@@ -10,18 +10,5 @@ word_size = 1
num_words = 16
tech_name = OPTS.tech_name
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
if tech_name.startswith("scn"):
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"
else:
supply_voltages = [1.0]
drc_name = "calibre"
lvs_name = "calibre"
pex_name = "calibre"