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https://github.com/VLSIDA/OpenRAM.git
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no wl for col end
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jcirimel
@@ -267,96 +267,74 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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for port in self.all_ports:
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for bit in self.all_ports:
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if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
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#if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
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self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
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if bit != port:
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self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
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else:
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self.rbl_wordline_names[port].append("rbl_wl0_{0}_{1}".format(port, bit))
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self.rbl_wordline_names[port].append("rbl_wl1_{0}_{1}".format(port, bit))
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if bit != port:
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self.gnd_wordline_names.append("rbl0_wl_{0}_{1}".format(port, bit))
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self.gnd_wordline_names.append("rbl1_wl_{0}_{1}".format(port, bit))
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#else:
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# self.rbl_wordline_names[port].append("rbl_wl0_{0}_{1}".format(port, bit))
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# self.rbl_wordline_names[port].append("rbl_wl1_{0}_{1}".format(port, bit))
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# if bit != port:
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# self.gnd_wordline_names.append("rbl0_wl_{0}_{1}".format(port, bit))
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# self.gnd_wordline_names.append("rbl1_wl_{0}_{1}".format(port, bit))
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self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
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self.wordline_names = self.bitcell_array.wordline_names
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self.all_wordline_names = self.bitcell_array.all_wordline_names
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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else:
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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self.replica_array_wordline_names.extend(["gnd"] * 2)
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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self.replica_array_wordline_names.extend(["gnd"] *2)
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.supplies = ["vdd", "gnd"]
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else:
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self.supplies = ["vpwr", "vgnd"]
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# Used for names/dimensions only
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.cell = factory.create(module_type="bitcell")
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else:
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self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
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# Replica columns
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self.replica_col_insts = []
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for port in self.all_ports:
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if port in self.rbls:
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
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else:
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self.replica_col_insts.append(None)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_insts = []
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# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
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for port in self.all_ports:
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self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row))
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self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
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# Top/bottom dummy rows or col caps
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.supplies = ["vdd", "gnd"]
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# Used for names/dimensions only
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self.cell = factory.create(module_type="bitcell")
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
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# Replica columns
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self.replica_col_insts = []
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for port in self.all_ports:
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if port in self.rbls:
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
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else:
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self.replica_col_insts.append(None)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_insts = []
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# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
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for port in self.all_ports:
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self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row))
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self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
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# Top/bottom dummy rows or col caps
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap))
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@@ -374,22 +352,9 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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mod=self.row_cap_right))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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else:
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap_bottom))
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self.connect_inst(self.all_bitline_names + self.supplies)
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
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mod=self.col_cap_top))
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self.connect_inst(self.all_bitline_names + self.supplies)
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from tech import custom_replica_bitcell_array_arrangement
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custom_replica_bitcell_array_arrangement(self)
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# Left/right Dummy columns
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self.dummy_col_insts = []
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
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mod=self.row_cap_left))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
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mod=self.row_cap_right))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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def create_layout(self):
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# We will need unused wordlines grounded, so we need to know their layer
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