diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index a5d40463..2e21c1ec 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -45,8 +45,7 @@ class _bitcell: cell_s8_6t = _cell({'bl' : 'bl0', 'br' : 'bl1', - 'wl0': 'wl0', - 'wl1': 'wl1'}) + 'wl': 'wl'}) cell_6t = _cell({'bl' : 'bl', 'br' : 'br', @@ -181,4 +180,4 @@ class cell_properties(): if ports == "{}R_{}W_{}RW".format(OPTS.num_r_ports, OPTS.num_w_ports, OPTS.num_rw_ports): use_custom_arrangement = True break - return use_custom_arrangement \ No newline at end of file + return use_custom_arrangement diff --git a/compiler/custom/s8_bitcell.py b/compiler/custom/s8_bitcell.py index 2905924a..fff3a6b8 100644 --- a/compiler/custom/s8_bitcell.py +++ b/compiler/custom/s8_bitcell.py @@ -27,11 +27,11 @@ class s8_bitcell(bitcell_base.bitcell_base): pin_names = ["bl0", "bl1", "wl0", "wl1", "vpwr", "vgnd"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] else: - pin_names = [props.bitcell.cell_6t.pin.bl, - props.bitcell.cell_6t.pin.br, - props.bitcell.cell_6t.pin.wl, - props.bitcell.cell_6t.pin.vdd, - props.bitcell.cell_6t.pin.gnd] + pin_names = [props.bitcell.cell_s8_6t.pin.bl, + props.bitcell.cell_s8_6t.pin.br, + props.bitcell.cell_s8_6t.pin.wl, + "vpwr", + "vgnd"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Q_bar'] @@ -61,15 +61,12 @@ class s8_bitcell(bitcell_base.bitcell_base): layer["mem"], "s8sram_cell\x00") - - #debug.check(OPTS.tech_name != "sky130", "sky130 does not yet support single port cells") - def get_all_wl_names(self): """ Creates a list of all wordline pin names """ if props.compare_ports(props.bitcell.split_wl): row_pins = ["wl0", "wl1"] else: - row_pins = [props.bitcell.s8_sp.pin.wl] + row_pins = [props.bitcell.cell_s8_6t.pin.wl] return row_pins def get_all_bitline_names(self): diff --git a/compiler/custom/s8_col_cap_array.py b/compiler/custom/s8_col_cap_array.py index 9b275fbd..3fb00a20 100644 --- a/compiler/custom/s8_col_cap_array.py +++ b/compiler/custom/s8_col_cap_array.py @@ -21,6 +21,7 @@ class s8_col_cap_array(design.design): self.column_offset = column_offset self.mirror = mirror self.no_instances = True + self.all_wordline_names = [] self.create_netlist() if not OPTS.netlist_only: self.create_layout() diff --git a/compiler/custom/s8_col_end.py b/compiler/custom/s8_col_end.py index 827692f0..5c9c4b92 100644 --- a/compiler/custom/s8_col_end.py +++ b/compiler/custom/s8_col_end.py @@ -21,8 +21,8 @@ class s8_col_end(design.design): type_list = [] if version == "colend": - self.name = "s8sram16x16_colenda" - structure = "s8sram16x16_colenda\x00" + self.name = "s8sram16x16_colend" + structure = "s8sram16x16_colend" elif version == "colend_p_cent": self.name = "s8sram16x16_colend_p_cent" structure = "s8sram16x16_colend_p_cent\x00" diff --git a/compiler/custom/s8_dummy_bitcell.py b/compiler/custom/s8_dummy_bitcell.py index fd2e407a..c6880638 100644 --- a/compiler/custom/s8_dummy_bitcell.py +++ b/compiler/custom/s8_dummy_bitcell.py @@ -24,11 +24,11 @@ class s8_dummy_bitcell(bitcell_base.bitcell_base): pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"] else: - pin_names = [props.bitcell.cell_6t.pin.bl, - props.bitcell.cell_6t.pin.br, - props.bitcell.cell_6t.pin.wl, - props.bitcell.cell_6t.pin.vdd, - props.bitcell.cell_6t.pin.gnd] + pin_names = [props.bitcell.cell_s8_6t.pin.bl, + props.bitcell.cell_s8_6t.pin.br, + props.bitcell.cell_s8_6t.pin.wl, + "vpwr", + "vgnd"] diff --git a/compiler/custom/s8_row_cap_array.py b/compiler/custom/s8_row_cap_array.py index da673f93..ab3dce1c 100644 --- a/compiler/custom/s8_row_cap_array.py +++ b/compiler/custom/s8_row_cap_array.py @@ -130,10 +130,9 @@ class s8_row_cap_array(design.design): def add_pins(self): - for row in range(self.rows): + for row in range(self.rows - 2): for port in self.all_ports: - self.add_pin("wl0_{}_{}".format(port, row), "OUTPUT") - self.add_pin("wl1_{}_{}".format(port, row), "OUTPUT") + self.add_pin("wl_{}_{}".format(port, row), "OUTPUT") self.add_pin("vpwr", "POWER") self.add_pin("vgnd", "GROUND") diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 99eca707..ffc3bb0f 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -56,31 +56,29 @@ class bitcell_base_array(design.design): # def get_all_wordline_names(self, prefix=""): # return [prefix + x for x in self.all_wordline_names] - def create_all_wordline_names(self): - for row in range(self.row_size): + def create_all_wordline_names(self, remove_wordline = 0): + for row in range(self.row_size - remove_wordline): for port in self.all_ports: if not cell_properties.compare_ports(cell_properties.bitcell.split_wl): self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) else: self.wordline_names[port].append("wl0_{0}_{1}".format(port, row)) self.wordline_names[port].append("wl1_{0}_{1}".format(port, row)) + self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl] - + def add_pins(self): + for bl_name in self.get_bitline_names(): + self.add_pin(bl_name, "INOUT") + for wl_name in self.get_wordline_names(): + self.add_pin(wl_name, "INPUT") if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): - for bl_name in self.get_bitline_names(): - self.add_pin(bl_name, "INOUT") - for wl_name in self.get_wordline_names(): - self.add_pin(wl_name, "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") else: - for bl_name in self.get_bitline_names(): - self.add_pin(bl_name, "INOUT") - for wl_name in self.get_wordline_names(): - self.add_pin(wl_name, "INPUT") self.add_pin("vpwr", "POWER") self.add_pin("vgnd", "GROUND") + def get_bitcell_pins(self, row, col): """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """ diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 39579b12..3a7a2ec0 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -98,7 +98,7 @@ class dummy_array(bitcell_base_array): height=self.height) wl_names = self.cell.get_all_wl_names() - if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement): + if not props.compare_ports(props.bitcell.split_wl): for row in range(self.row_size): for port in self.all_ports: wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port]) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index ec27ba32..816a5391 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -267,96 +267,74 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): for port in self.all_ports: for bit in self.all_ports: - if not cell_properties.compare_ports(cell_properties.bitcell.split_wl): + #if not cell_properties.compare_ports(cell_properties.bitcell.split_wl): self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit)) if bit != port: self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit)) - else: - self.rbl_wordline_names[port].append("rbl_wl0_{0}_{1}".format(port, bit)) - self.rbl_wordline_names[port].append("rbl_wl1_{0}_{1}".format(port, bit)) - if bit != port: - self.gnd_wordline_names.append("rbl0_wl_{0}_{1}".format(port, bit)) - self.gnd_wordline_names.append("rbl1_wl_{0}_{1}".format(port, bit)) + #else: + # self.rbl_wordline_names[port].append("rbl_wl0_{0}_{1}".format(port, bit)) + # self.rbl_wordline_names[port].append("rbl_wl1_{0}_{1}".format(port, bit)) + # if bit != port: + # self.gnd_wordline_names.append("rbl0_wl_{0}_{1}".format(port, bit)) + # self.gnd_wordline_names.append("rbl1_wl_{0}_{1}".format(port, bit)) self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl] self.wordline_names = self.bitcell_array.wordline_names self.all_wordline_names = self.bitcell_array.all_wordline_names + + # All wordlines including dummy and RBL + self.replica_array_wordline_names = [] if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): - - # All wordlines including dummy and RBL - self.replica_array_wordline_names = [] self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names())) - for bit in range(self.rbl[0]): - self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]]) - self.replica_array_wordline_names.extend(self.all_wordline_names) - for bit in range(self.rbl[1]): - self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]]) + for bit in range(self.rbl[0]): + self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]]) + self.replica_array_wordline_names.extend(self.all_wordline_names) + for bit in range(self.rbl[1]): + self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]]) + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names())) - for port in range(self.rbl[0]): - self.add_pin(self.rbl_wordline_names[port][port], "INPUT") - self.add_pin_list(self.all_wordline_names, "INPUT") - for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]): - self.add_pin(self.rbl_wordline_names[port][port], "INPUT") - else: - # All wordlines including dummy and RBL - self.replica_array_wordline_names = [] - self.replica_array_wordline_names.extend(["gnd"] * 2) - for bit in range(self.rbl[0]): - self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]]) - self.replica_array_wordline_names.extend(self.all_wordline_names) - for bit in range(self.rbl[1]): - self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]]) - self.replica_array_wordline_names.extend(["gnd"] *2) - - for port in range(self.rbl[0]): - self.add_pin(self.rbl_wordline_names[port][port], "INPUT") - self.add_pin_list(self.all_wordline_names, "INPUT") - for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]): - self.add_pin(self.rbl_wordline_names[port][port], "INPUT") + for port in range(self.rbl[0]): + self.add_pin(self.rbl_wordline_names[port][port], "INPUT") + self.add_pin_list(self.all_wordline_names, "INPUT") + for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]): + self.add_pin(self.rbl_wordline_names[port][port], "INPUT") def create_instances(self): """ Create the module instances used in this design """ - - if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): - self.supplies = ["vdd", "gnd"] - else: - self.supplies = ["vpwr", "vgnd"] - - # Used for names/dimensions only - if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): - self.cell = factory.create(module_type="bitcell") - else: - self.cell = factory.create(module_type="s8_bitcell", version = "opt1") - - # Main array - self.bitcell_array_inst=self.add_inst(name="bitcell_array", - mod=self.bitcell_array) - self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies) - - # Replica columns - self.replica_col_insts = [] - for port in self.all_ports: - if port in self.rbls: - self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port), - mod=self.replica_columns[port])) - self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies) - else: - self.replica_col_insts.append(None) - - # Dummy rows under the bitcell array (connected with with the replica cell wl) - self.dummy_row_replica_insts = [] - # Note, this is the number of left and right even if we aren't adding the columns to this bitcell array! - for port in self.all_ports: - self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port), - mod=self.dummy_row)) - self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies) - - # Top/bottom dummy rows or col caps if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): + self.supplies = ["vdd", "gnd"] + + # Used for names/dimensions only + self.cell = factory.create(module_type="bitcell") + + # Main array + self.bitcell_array_inst=self.add_inst(name="bitcell_array", + mod=self.bitcell_array) + self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies) + + # Replica columns + self.replica_col_insts = [] + for port in self.all_ports: + if port in self.rbls: + self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port), + mod=self.replica_columns[port])) + self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies) + else: + self.replica_col_insts.append(None) + + # Dummy rows under the bitcell array (connected with with the replica cell wl) + self.dummy_row_replica_insts = [] + # Note, this is the number of left and right even if we aren't adding the columns to this bitcell array! + for port in self.all_ports: + self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port), + mod=self.dummy_row)) + self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies) + + # Top/bottom dummy rows or col caps self.dummy_row_insts = [] self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot", mod=self.col_cap)) @@ -374,22 +352,9 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): mod=self.row_cap_right)) self.connect_inst(self.replica_array_wordline_names + self.supplies) else: - self.dummy_row_insts = [] - self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot", - mod=self.col_cap_bottom)) - self.connect_inst(self.all_bitline_names + self.supplies) - self.dummy_row_insts.append(self.add_inst(name="dummy_row_top", - mod=self.col_cap_top)) - self.connect_inst(self.all_bitline_names + self.supplies) + from tech import custom_replica_bitcell_array_arrangement + custom_replica_bitcell_array_arrangement(self) - # Left/right Dummy columns - self.dummy_col_insts = [] - self.dummy_col_insts.append(self.add_inst(name="dummy_col_left", - mod=self.row_cap_left)) - self.connect_inst(self.replica_array_wordline_names + self.supplies) - self.dummy_col_insts.append(self.add_inst(name="dummy_col_right", - mod=self.row_cap_right)) - self.connect_inst(self.replica_array_wordline_names + self.supplies) def create_layout(self): # We will need unused wordlines grounded, so we need to know their layer diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 929a37e3..9988096c 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -62,7 +62,11 @@ class replica_column(bitcell_base_array): def add_pins(self): self.create_all_bitline_names() - self.create_all_wordline_names() + #remove 2 wordlines to account for top/bot + if not cell_properties.bitcell.end_caps: + self.create_all_wordline_names() + else: + self.create_all_wordline_names(2) self.add_pin_list(self.all_bitline_names, "OUTPUT") self.add_pin_list(self.all_wordline_names, "INPUT") diff --git a/compiler/tests/missing_pin.gds b/compiler/tests/missing_pin.gds index 25df96f6..692677d9 100644 Binary files a/compiler/tests/missing_pin.gds and b/compiler/tests/missing_pin.gds differ diff --git a/compiler/tests/sram_1b_16_1rw_sky130.log b/compiler/tests/sram_1b_16_1rw_sky130.log index 4fd3c1ee..e92e1a3b 100644 --- a/compiler/tests/sram_1b_16_1rw_sky130.log +++ b/compiler/tests/sram_1b_16_1rw_sky130.log @@ -1,1761 +1,4 @@ -[globals/init_openram]: Initializing OpenRAM... -[globals/setup_paths]: Temporary files saved in /home/jesse/output/ -[globals/read_config]: Configuration file is /home/jesse/openram/compiler/tests/configs/config.py -[globals/read_config]: Output saved in /home/jesse/openram/compiler/tests/./ -[globals/import_tech]: Adding technology path: /home/jesse/openram/technology -[globals/init_paths]: Creating temp directory: /home/jesse/output/ -[characterizer/]: Initializing characterizer... -[characterizer/]: Analytical model enabled. -[verify/]: Initializing verify... -[verify/]: Finding DRC/LVS/PEX tools. -[globals/get_tool]: Using DRC: /usr/local/bin/magic -[globals/get_tool]: Using LVS: /usr/local/bin/netgen -[globals/get_tool]: Using PEX: /usr/local/bin/magic -[globals/get_tool]: Using GDS: /usr/local/bin/magic -[bitcell_base_array/__init__]: Creating replica_bitcell_array 4 x 4 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array 4 x 4 -[bitcell_base_array/__init__]: Creating bitcell_array 4 x 4 -[bitcell_base_array/__init__]: Creating dummy_array 1 x 4 -[verify.magic/run_drc]: Cell replica_bitcell_array has 2074 error tiles. -WARNING: file magic.py: line 210: DRC Errors replica_bitcell_array 2074 +WARNING: file magic.py: line 210: DRC Errors replica_bitcell_array 985 -[verify.magic/run_lvs]: Flattening unmatched subcell s8sram_cell in circuit s8sram_cell_opt1_ce (0)(1 instance) -[verify.magic/run_lvs]: Flattening unmatched subcell s8sram16x16_colend_ce in circuit s8sram16x16_colenda (0)(1 instance) -[verify.magic/run_lvs]: Flattening unmatched subcell s8sram_cell_opt1_ce in circuit s8sram_cell_opt1a (0)(1 instance) -[verify.magic/run_lvs]: Flattening unmatched subcell s8sram_cell_opt1_ce in circuit s8sram_cell_opt1 (0)(1 instance) -[verify.magic/run_lvs]: Flattening unmatched subcell s8_col_cap_array in circuit replica_bitcell_array (0)(1 instance) -[verify.magic/run_lvs]: Flattening unmatched subcell s8_row_cap_array in circuit replica_bitcell_array (0)(1 instance) -[verify.magic/run_lvs]: Flattening unmatched subcell s8_row_cap_array_0 in circuit replica_bitcell_array (0)(1 instance) -[verify.magic/run_lvs]: Flattening unmatched subcell s8_col_cap_array_0 in circuit replica_bitcell_array (0)(1 instance) -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: s8sram_colend_met2_0/m2_0_4# -[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: s8sram_colend_met2_0/m2_0_236# -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: bl0 -[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: bl1 -[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: vpwr -[verify.magic/run_lvs]: Cell s8sram16x16_colenda disconnected node: vgnd -[verify.magic/run_lvs]: Equate pins: cell s8sram16x16_colenda and/or s8sram16x16_colenda has no elements. -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: s8sram_cell_met2_0/m2_0_59# -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: bl0 -[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: bl1 -[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: wl0 -[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: wl1 -[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: vpwr -[verify.magic/run_lvs]: Cell s8sram_cell_opt1a disconnected node: vgnd -[verify.magic/run_lvs]: Equate pins: cell s8sram_cell_opt1a and/or s8sram_cell_opt1a has no elements. -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: s8sram_cell_met2_0/m2_0_59# -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: bl0 -[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: bl1 -[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: wl0 -[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: wl1 -[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: vpwr -[verify.magic/run_lvs]: Cell s8sram_cell_opt1 disconnected node: vgnd -[verify.magic/run_lvs]: Equate pins: cell s8sram_cell_opt1 and/or s8sram_cell_opt1 has no elements. -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/polygon00010_0/m1_42_0# -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/a_113_124# -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/a_113_124# -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/a_113_143# -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell dummy_array disconnected node: vpwr -[verify.magic/run_lvs]: Cell dummy_array disconnected node: vgnd -[verify.magic/run_lvs]: Class dummy_array: Merged 1 devices. -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/polygon00010_0/m1_42_0# -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/a_113_124# -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/a_113_124# -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/a_113_143# -[verify.magic/run_lvs]: Cell dummy_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell dummy_array disconnected node: vpwr -[verify.magic/run_lvs]: Cell dummy_array disconnected node: vgnd -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Subcircuit summary: -[verify.magic/run_lvs]: Circuit 1: dummy_array |Circuit 2: dummy_array -[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- -[verify.magic/run_lvs]: s8sram_cell_opt1a (4) |s8sram_cell_opt1a (4) -[verify.magic/run_lvs]: s8sram_wlstrap (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) -[verify.magic/run_lvs]: Number of devices: 6 **Mismatch** |Number of devices: 4 **Mismatch** -[verify.magic/run_lvs]: Number of nets: 20 **Mismatch** |Number of nets: 15 **Mismatch** -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: NET mismatches: Class fragments follow (with fanout counts): -[verify.magic/run_lvs]: Circuit 1: dummy_array |Circuit 2: dummy_array -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: bl0_0_3 |Net: col_0_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 1 | s8sram_cell_opt1a/bl0 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: bl0_0_2 |Net: col_1_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 1 | s8sram_cell_opt1a/bl0 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: bl0_0_1 |Net: col_2_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 1 | s8sram_cell_opt1a/bl0 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: bl0_0_0 |Net: col_3_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 1 | s8sram_cell_opt1a/bl0 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: bl1_0_3 |Net: bl_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 1 | s8sram_cell_opt1a/bl1 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: bl1_0_2 |Net: bl_0_1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 1 | s8sram_cell_opt1a/bl1 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: bl1_0_1 |Net: bl_0_2 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 1 | s8sram_cell_opt1a/bl1 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: bl1_0_0 |Net: bl_0_3 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 1 | s8sram_cell_opt1a/bl1 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_1674_61# |Net: br_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_1174_61# |Net: br_0_1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_674_61# |Net: br_0_2 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_38_62# |Net: br_0_3 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_1538_220# |Net: wl0_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | s8sram_cell_opt1a/wl1 = 4 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_1038_220# |Net: wl1_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | s8sram_cell_opt1a/vpwr = 4 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_538_220# |Net: vdd -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | s8sram_cell_opt1a/vgnd = 4 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_38_220# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: vpwr |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/vgnd = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/vpwr = 4 | -[verify.magic/run_lvs]: s8sram_wlstrap/1 = 1 | -[verify.magic/run_lvs]: s8sram16x16_wlstrap_p/1 = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_0/vpb |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/vpb = 4 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: VSUBS |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/vnb = 4 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: wl0_0_0 |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: DEVICE mismatches: Class fragments follow (with node fanout counts): -[verify.magic/run_lvs]: Circuit 1: dummy_array |Circuit 2: dummy_array -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: s8sram_wlstrap_0 |(no matching instance) -[verify.magic/run_lvs]: 1 = 10 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram16x16_wlstrap_p_0 |(no matching instance) -[verify.magic/run_lvs]: 1 = 10 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_3 |Instance: s8sram_cell_opt1arow_0, -[verify.magic/run_lvs]: bl0 = 1 | bl0 = 1 -[verify.magic/run_lvs]: bl1 = 1 | bl1 = 1 -[verify.magic/run_lvs]: vgnd = 10 | wl0 = 1 -[verify.magic/run_lvs]: vpwr = 10 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 4 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 4 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 4 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_2 |Instance: s8sram_cell_opt1arow_0, -[verify.magic/run_lvs]: bl0 = 1 | bl0 = 1 -[verify.magic/run_lvs]: bl1 = 1 | bl1 = 1 -[verify.magic/run_lvs]: vgnd = 10 | wl0 = 1 -[verify.magic/run_lvs]: vpwr = 10 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 4 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 4 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 4 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_1 |Instance: s8sram_cell_opt1arow_0, -[verify.magic/run_lvs]: bl0 = 1 | bl0 = 1 -[verify.magic/run_lvs]: bl1 = 1 | bl1 = 1 -[verify.magic/run_lvs]: vgnd = 10 | wl0 = 1 -[verify.magic/run_lvs]: vpwr = 10 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 4 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 4 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 4 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_0 |Instance: s8sram_cell_opt1arow_0, -[verify.magic/run_lvs]: bl0 = 1 | bl0 = 1 -[verify.magic/run_lvs]: bl1 = 1 | bl1 = 1 -[verify.magic/run_lvs]: vgnd = 10 | wl0 = 1 -[verify.magic/run_lvs]: vpwr = 10 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 4 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 4 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 4 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Netlists do not match. -[verify.magic/run_lvs]: Flattening non-matched subcircuits dummy_array dummy_array -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/polygon00010_0/m1_42_0# -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/a_113_124# -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/a_113_124# -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/a_113_143# -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: vpwr -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: vgnd -[verify.magic/run_lvs]: Class bitcell_array: Merged 10 devices. -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/polygon00010_0/m1_42_0# -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/a_113_124# -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/a_113_124# -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_0/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram16x16_wlstrap_p_0/s8sram16x16_wlstrap_p_ce_0/a_113_143# -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: s8sram_wlstrap_1/s8sram_wlstrap_ce_0/polygon00006_0/m1_158_122# -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: vpwr -[verify.magic/run_lvs]: Cell bitcell_array disconnected node: vgnd -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Subcircuit summary: -[verify.magic/run_lvs]: Circuit 1: bitcell_array |Circuit 2: bitcell_array -[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- -[verify.magic/run_lvs]: s8sram_cell_opt1a (8) |s8sram_cell_opt1a (8) -[verify.magic/run_lvs]: s8sram_wlstrap (1) |(no matching element) -[verify.magic/run_lvs]: s8sram_cell_opt1 (8) |s8sram_cell_opt1 (8) -[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) -[verify.magic/run_lvs]: Number of devices: 18 **Mismatch** |Number of devices: 16 **Mismatch** -[verify.magic/run_lvs]: Number of nets: 43 **Mismatch** |Number of nets: 21 **Mismatch** -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: NET mismatches: Class fragments follow (with fanout counts): -[verify.magic/run_lvs]: Circuit 1: bitcell_array |Circuit 2: bitcell_array -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: bl1_0_3 |Net: vdd -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1a/vgnd = 8 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | s8sram_cell_opt1/vgnd = 8 -[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: bl1_0_2 |Net: col_0_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1a/bl0 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | s8sram_cell_opt1/bl0 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: bl1_0_1 |Net: col_1_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1a/bl0 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | s8sram_cell_opt1/bl0 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: bl1_0_0 |Net: col_2_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1a/bl0 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | s8sram_cell_opt1/bl0 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: vpwr |Net: col_3_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/vgnd = 8 | s8sram_cell_opt1a/bl0 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1a/vpwr = 8 | s8sram_cell_opt1/bl0 = 2 -[verify.magic/run_lvs]: s8sram_wlstrap/1 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1/vgnd = 8 | -[verify.magic/run_lvs]: s8sram_cell_opt1/vpwr = 8 | -[verify.magic/run_lvs]: s8sram16x16_wlstrap_p/1 = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_0/vpb |Net: bl_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/vpb = 8 | s8sram_cell_opt1a/bl1 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1/vpb = 8 | s8sram_cell_opt1/bl1 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: VSUBS |Net: bl_0_1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/vnb = 8 | s8sram_cell_opt1a/bl1 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1/vnb = 8 | s8sram_cell_opt1/bl1 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_0/s8sram_cell_opt1_ |Net: bl_0_2 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/bl1 = 2 -[verify.magic/run_lvs]: | s8sram_cell_opt1/bl1 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_1/s8sram_cell_opt1_ |Net: bl_0_3 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/bl1 = 2 -[verify.magic/run_lvs]: | s8sram_cell_opt1/bl1 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_2/s8sram_cell_opt1_ |Net: br_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 2 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_3/s8sram_cell_opt1_ |Net: br_0_1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 2 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_4/s8sram_cell_opt1_ |Net: br_0_2 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 2 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_5/s8sram_cell_opt1_ |Net: br_0_3 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 2 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_6/s8sram_cell_opt1_ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_7/s8sram_cell_opt1_ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_0/s8sram_cell_opt1_ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_1/s8sram_cell_opt1_ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_2/s8sram_cell_opt1_ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_3/s8sram_cell_opt1_ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_4/s8sram_cell_opt1_ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_5/s8sram_cell_opt1_ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_6/s8sram_cell_opt1_ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1a_7/s8sram_cell_opt1_ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_0/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_1/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_2/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_3/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_4/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_5/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_6/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_7/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_0/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_1/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_2/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_3/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_4/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_5/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_6/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_7/s8sram_cell_opt1_c |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_3 -[verify.magic/run_lvs]: | s8sram_cell_opt1/vpwr = 4 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_1 -[verify.magic/run_lvs]: | s8sram_cell_opt1/vpwr = 4 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_3 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 4 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_1 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 4 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_2 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 4 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_0 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 4 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_2 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 4 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_0 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 4 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: wl0_0_1 |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: wl0_0_3 |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: wl0_0_0 |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: wl0_0_2 |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: DEVICE mismatches: Class fragments follow (with node fanout counts): -[verify.magic/run_lvs]: Circuit 1: bitcell_array |Circuit 2: bitcell_array -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: s8sram_wlstrap_0 |(no matching instance) -[verify.magic/run_lvs]: 1 = 34 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram16x16_wlstrap_p_0 |(no matching instance) -[verify.magic/run_lvs]: 1 = 34 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_7 |Instance: s8sram_cell_opt1row_3, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_6 |Instance: s8sram_cell_opt1row_3, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_5 |Instance: s8sram_cell_opt1row_3, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_4 |Instance: s8sram_cell_opt1row_3, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_3 |Instance: s8sram_cell_opt1row_1, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_2 |Instance: s8sram_cell_opt1row_1, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_1 |Instance: s8sram_cell_opt1row_1, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_0 |Instance: s8sram_cell_opt1row_1, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_7 |Instance: s8sram_cell_opt1arow_2, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_6 |Instance: s8sram_cell_opt1arow_2, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_5 |Instance: s8sram_cell_opt1arow_2, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_4 |Instance: s8sram_cell_opt1arow_2, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_3 |Instance: s8sram_cell_opt1arow_0, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_2 |Instance: s8sram_cell_opt1arow_0, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_1 |Instance: s8sram_cell_opt1arow_0, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_0 |Instance: s8sram_cell_opt1arow_0, -[verify.magic/run_lvs]: bl0 = 8 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 8 | bl1 = 4 -[verify.magic/run_lvs]: vgnd = 34 | wl0 = 4 -[verify.magic/run_lvs]: vpwr = 34 | wl1 = 4 -[verify.magic/run_lvs]: vpb = 16 | vpwr = 4 -[verify.magic/run_lvs]: wl1 = 12 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 12 | -[verify.magic/run_lvs]: vnb = 16 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 12 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Netlists do not match. -[verify.magic/run_lvs]: Flattening non-matched subcircuits bitcell_array bitcell_arrayClass replica_column: Merged 4 devices. -[verify.magic/run_lvs]: Class replica_column: Merged 1 devices. -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Subcircuit summary: -[verify.magic/run_lvs]: Circuit 1: replica_column |Circuit 2: replica_column -[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- -[verify.magic/run_lvs]: s8sram_cell_opt1a (2) |s8sram_cell_opt1a (2) -[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent (1) |(no matching element) -[verify.magic/run_lvs]: s8sram_cell_opt1 (3) |s8sram_cell_opt1 (3) -[verify.magic/run_lvs]: s8sram16x16_colenda (2) |s8sram16x16_colenda (1) **Mismatch** -[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_colend_p_cent (1) |(no matching element) -[verify.magic/run_lvs]: Number of devices: 10 **Mismatch** |Number of devices: 6 **Mismatch** -[verify.magic/run_lvs]: Number of nets: 22 **Mismatch** |Number of nets: 14 **Mismatch** -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Flattening instances of s8sram16x16_colenda in cell replica_column makes a better match -[verify.magic/run_lvs]: Flattening instances of s8sram16x16_colenda in cell replica_column makes a better match -[verify.magic/run_lvs]: Making another compare attempt. -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Subcircuit summary: -[verify.magic/run_lvs]: Circuit 1: replica_column |Circuit 2: replica_column -[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- -[verify.magic/run_lvs]: s8sram_cell_opt1a (2) |s8sram_cell_opt1a (2) -[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent (1) |(no matching element) -[verify.magic/run_lvs]: s8sram_cell_opt1 (3) |s8sram_cell_opt1 (3) -[verify.magic/run_lvs]: nshort (2) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_colend_p_cent (1) |(no matching element) -[verify.magic/run_lvs]: Number of devices: 10 **Mismatch** |Number of devices: 5 **Mismatch** -[verify.magic/run_lvs]: Number of nets: 22 **Mismatch** |Number of nets: 14 **Mismatch** -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: NET mismatches: Class fragments follow (with fanout counts): -[verify.magic/run_lvs]: Circuit 1: replica_column |Circuit 2: replica_column -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: br_0_0 |Net: wl0_0_1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1/wl0 = 1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 3 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 3 | -[verify.magic/run_lvs]: nshort/(drain|source) = 4 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: vgnd |Net: wl0_0_3 -[verify.magic/run_lvs]: s8sram_cell_opt1a/vgnd = 2 | s8sram_cell_opt1/wl0 = 1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/vpwr = 2 | -[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/1 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1/vgnd = 3 | -[verify.magic/run_lvs]: s8sram_cell_opt1/vpwr = 3 | -[verify.magic/run_lvs]: s8sram16x16_wlstrap_p/1 = 1 | -[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/1 = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: wl_0_5 |Net: wl0_0_5 -[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 1 | s8sram_cell_opt1/wl0 = 1 -[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: wl_0_3 |Net: wl1_0_1 -[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 1 | s8sram_cell_opt1/wl1 = 1 -[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: wl_0_1 |Net: wl1_0_3 -[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 1 | s8sram_cell_opt1/wl1 = 1 -[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_38_1737# |Net: wl1_0_5 -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | s8sram_cell_opt1/wl1 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_38_1105# |Net: bl_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | s8sram_cell_opt1/bl0 = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/bl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_38_473# |Net: br_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | s8sram_cell_opt1/bl1 = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/bl1 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_38_1895# |Net: vdd -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | s8sram_cell_opt1/vpwr = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_38_1263# |Net: gnd -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | s8sram_cell_opt1/vgnd = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/vgnd = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_38_631# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram16x16_colend_p_cent_0/vpb |(no matching net) -[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/2 = 1 | -[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/2 = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_4 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_2 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 1 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_4 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl0 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_2 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl0 = 1 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: s8sram16x16_colenda_1/s8sram16x16_col |(no matching net) -[verify.magic/run_lvs]: nshort/gate = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram16x16_colenda_0/s8sram16x16_col |(no matching net) -[verify.magic/run_lvs]: nshort/gate = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: a_38_947# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_38_1579# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: a_38_789# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: a_38_1421# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: wl_0_2 |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: wl_0_4 |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: VSUBS |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/vnb = 2 | -[verify.magic/run_lvs]: s8sram_cell_opt1/vnb = 3 | -[verify.magic/run_lvs]: nshort/bulk = 2 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: s8sram_cell_opt1_0/vpb |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/vpb = 2 | -[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/3 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1/vpb = 3 | -[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/3 = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: DEVICE mismatches: Class fragments follow (with node fanout counts): -[verify.magic/run_lvs]: Circuit 1: replica_column |Circuit 2: replica_column -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: s8sram16x16_colenda_p_cent_0 |(no matching instance) -[verify.magic/run_lvs]: 1 = 13 | -[verify.magic/run_lvs]: 2 = 2 | -[verify.magic/run_lvs]: 3 = 7 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram16x16_wlstrap_p_0 |(no matching instance) -[verify.magic/run_lvs]: 1 = 13 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram16x16_colend_p_cent_0 |(no matching instance) -[verify.magic/run_lvs]: 1 = 13 | -[verify.magic/run_lvs]: 2 = 2 | -[verify.magic/run_lvs]: 3 = 7 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: s8sram16x16_colenda_1//s8sram16x |(no matching instance) -[verify.magic/run_lvs]: (drain,source) = (14,14) | -[verify.magic/run_lvs]: gate = 1 | -[verify.magic/run_lvs]: bulk = 7 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram16x16_colenda_0//s8sram16x |(no matching instance) -[verify.magic/run_lvs]: (drain,source) = (14,14) | -[verify.magic/run_lvs]: gate = 1 | -[verify.magic/run_lvs]: bulk = 7 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_2 |Instance: s8sram_cell_opt1rbc_5 -[verify.magic/run_lvs]: bl0 = 14 | bl0 = 5 -[verify.magic/run_lvs]: bl1 = 14 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 13 | wl0 = 1 -[verify.magic/run_lvs]: vpwr = 13 | wl1 = 1 -[verify.magic/run_lvs]: vpb = 7 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 3 | vgnd = 5 -[verify.magic/run_lvs]: wl0 = 3 | -[verify.magic/run_lvs]: vnb = 7 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 3 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_1 |Instance: s8sram_cell_opt1rbc_3 -[verify.magic/run_lvs]: bl0 = 14 | bl0 = 5 -[verify.magic/run_lvs]: bl1 = 14 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 13 | wl0 = 1 -[verify.magic/run_lvs]: vpwr = 13 | wl1 = 1 -[verify.magic/run_lvs]: vpb = 7 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 3 | vgnd = 5 -[verify.magic/run_lvs]: wl0 = 3 | -[verify.magic/run_lvs]: vnb = 7 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 3 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1_0 |Instance: s8sram_cell_opt1rbc_1 -[verify.magic/run_lvs]: bl0 = 14 | bl0 = 5 -[verify.magic/run_lvs]: bl1 = 14 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 13 | wl0 = 1 -[verify.magic/run_lvs]: vpwr = 13 | wl1 = 1 -[verify.magic/run_lvs]: vpb = 7 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 3 | vgnd = 5 -[verify.magic/run_lvs]: wl0 = 3 | -[verify.magic/run_lvs]: vnb = 7 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 3 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_0 |(no matching instance) -[verify.magic/run_lvs]: bl0 = 14 | -[verify.magic/run_lvs]: bl1 = 14 | -[verify.magic/run_lvs]: vgnd = 13 | -[verify.magic/run_lvs]: vpwr = 13 | -[verify.magic/run_lvs]: vpb = 7 | -[verify.magic/run_lvs]: wl1 = 3 | -[verify.magic/run_lvs]: wl0 = 3 | -[verify.magic/run_lvs]: vnb = 7 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 3 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8sram_cell_opt1a_1 |(no matching instance) -[verify.magic/run_lvs]: bl0 = 14 | -[verify.magic/run_lvs]: bl1 = 14 | -[verify.magic/run_lvs]: vgnd = 13 | -[verify.magic/run_lvs]: vpwr = 13 | -[verify.magic/run_lvs]: vpb = 7 | -[verify.magic/run_lvs]: wl1 = 3 | -[verify.magic/run_lvs]: wl0 = 3 | -[verify.magic/run_lvs]: vnb = 7 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 3 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching instance) |Instance: s8sram_cell_opt1arbc_2 -[verify.magic/run_lvs]: | bl0 = 5 -[verify.magic/run_lvs]: | bl1 = 5 -[verify.magic/run_lvs]: | wl0 = 1 -[verify.magic/run_lvs]: | wl1 = 1 -[verify.magic/run_lvs]: | vpwr = 5 -[verify.magic/run_lvs]: | vgnd = 5 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching instance) |Instance: s8sram_cell_opt1arbc_4 -[verify.magic/run_lvs]: | bl0 = 5 -[verify.magic/run_lvs]: | bl1 = 5 -[verify.magic/run_lvs]: | wl0 = 1 -[verify.magic/run_lvs]: | wl1 = 1 -[verify.magic/run_lvs]: | vpwr = 5 -[verify.magic/run_lvs]: | vgnd = 5 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Netlists do not match. -[verify.magic/run_lvs]: Flattening non-matched subcircuits replica_column replica_column -[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: vdd -[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: gnd -[verify.magic/run_lvs]: Class replica_bitcell_array: Merged 23 devices. -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: vdd -[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: gnd -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Subcircuit summary: -[verify.magic/run_lvs]: Circuit 1: replica_bitcell_array |Circuit 2: replica_bitcell_array -[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- -[verify.magic/run_lvs]: s8sram16x16_colenda (4) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_colend_p_cent (1) |(no matching element) -[verify.magic/run_lvs]: s8sram_cell_opt1a (14) |s8sram_cell_opt1a (14) -[verify.magic/run_lvs]: s8sram_wlstrap (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) -[verify.magic/run_lvs]: s8sram_cell_opt1 (11) |s8sram_cell_opt1 (11) -[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent (1) |(no matching element) -[verify.magic/run_lvs]: nshort (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_corner (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_cornera (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_rowenda (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_rowend (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_cornerb (1) |(no matching element) -[verify.magic/run_lvs]: Number of devices: 39 **Mismatch** |Number of devices: 25 **Mismatch** -[verify.magic/run_lvs]: Number of nets: 62 **Mismatch** |Number of nets: 32 **Mismatch** -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Flattening instances of s8sram16x16_colenda in cell replica_bitcell_array makes a better match -[verify.magic/run_lvs]: Flattening instances of s8sram16x16_colenda in cell replica_bitcell_array makes a better match -[verify.magic/run_lvs]: Making another compare attempt. -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: vdd -[verify.magic/run_lvs]: Cell replica_bitcell_array disconnected node: gnd -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: Subcircuit summary: -[verify.magic/run_lvs]: Circuit 1: replica_bitcell_array |Circuit 2: replica_bitcell_array -[verify.magic/run_lvs]: -------------------------------------------|------------------------------------------- -[verify.magic/run_lvs]: nshort (5) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_colend_p_cent (1) |(no matching element) -[verify.magic/run_lvs]: s8sram_cell_opt1a (14) |s8sram_cell_opt1a (14) -[verify.magic/run_lvs]: s8sram_wlstrap (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_wlstrap_p (1) |(no matching element) -[verify.magic/run_lvs]: s8sram_cell_opt1 (11) |s8sram_cell_opt1 (11) -[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_corner (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_cornera (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_rowenda (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_rowend (1) |(no matching element) -[verify.magic/run_lvs]: s8sram16x16_cornerb (1) |(no matching element) -[verify.magic/run_lvs]: Number of devices: 39 **Mismatch** |Number of devices: 25 **Mismatch** -[verify.magic/run_lvs]: Number of nets: 62 **Mismatch** |Number of nets: 32 **Mismatch** -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: NET mismatches: Class fragments follow (with fanout counts): -[verify.magic/run_lvs]: Circuit 1: replica_bitcell_array |Circuit 2: replica_bitcell_array -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: dummy_array_0/bl0_0_2 |Net: dummy_arraydummy_row_0/col_0_bitcell -[verify.magic/run_lvs]: nshort/(drain|source) = 2 | s8sram_cell_opt1a/bl0 = 1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 3 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 3 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: dummy_array_0/bl0_0_3 |Net: dummy_arraydummy_row_0/col_1_bitcell -[verify.magic/run_lvs]: nshort/(drain|source) = 2 | s8sram_cell_opt1a/bl0 = 1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 3 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 3 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: dummy_array_0/bl0_0_0 |Net: dummy_arraydummy_row_0/col_2_bitcell -[verify.magic/run_lvs]: nshort/(drain|source) = 2 | s8sram_cell_opt1a/bl0 = 1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 3 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 3 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: dummy_array_0/bl0_0_1 |Net: dummy_arraydummy_row_0/col_3_bitcell -[verify.magic/run_lvs]: nshort/(drain|source) = 2 | s8sram_cell_opt1a/bl0 = 1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 3 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 3 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 2 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 2 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: rbl_bl_0_0 |Net: bl_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl0 = 2 | s8sram_cell_opt1a/bl1 = 3 -[verify.magic/run_lvs]: s8sram_cell_opt1a/bl1 = 2 | s8sram_cell_opt1/bl1 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1/bl0 = 3 | -[verify.magic/run_lvs]: s8sram_cell_opt1/bl1 = 3 | -[verify.magic/run_lvs]: nshort/(drain|source) = 2 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: VSUBS |Net: bl_0_1 -[verify.magic/run_lvs]: nshort/bulk = 5 | s8sram_cell_opt1a/bl1 = 3 -[verify.magic/run_lvs]: s8sram_cell_opt1a/vnb = 14 | s8sram_cell_opt1/bl1 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1/vnb = 11 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: rbl_wl1_0_0 |Net: bl_0_2 -[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/1 = 1 | s8sram_cell_opt1a/bl1 = 3 -[verify.magic/run_lvs]: s8sram_cell_opt1a/vgnd = 14 | s8sram_cell_opt1/bl1 = 2 -[verify.magic/run_lvs]: s8sram_cell_opt1a/vpwr = 14 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 4 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | -[verify.magic/run_lvs]: s8sram_wlstrap/1 = 1 | -[verify.magic/run_lvs]: s8sram16x16_wlstrap_p/1 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1/vgnd = 11 | -[verify.magic/run_lvs]: s8sram_cell_opt1/vpwr = 11 | -[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/1 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | -[verify.magic/run_lvs]: s8sram16x16_corner/1 = 1 | -[verify.magic/run_lvs]: s8sram16x16_cornera/2 = 1 | -[verify.magic/run_lvs]: s8sram16x16_rowenda/1 = 1 | -[verify.magic/run_lvs]: s8sram16x16_rowenda/2 = 1 | -[verify.magic/run_lvs]: s8sram16x16_rowend/1 = 1 | -[verify.magic/run_lvs]: s8sram16x16_rowend/2 = 1 | -[verify.magic/run_lvs]: s8sram16x16_cornerb/1 = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: dummy_array_0/s8sram_cell_opt1a_0/vpb |Net: bl_0_3 -[verify.magic/run_lvs]: nshort/gate = 5 | s8sram_cell_opt1a/bl1 = 3 -[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/2 = 1 | s8sram_cell_opt1/bl1 = 2 -[verify.magic/run_lvs]: s8sram16x16_colend_p_cent/3 = 1 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/vpb = 14 | -[verify.magic/run_lvs]: s8sram_cell_opt1/vpb = 11 | -[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/2 = 1 | -[verify.magic/run_lvs]: s8sram16x16_colenda_p_cent/3 = 1 | -[verify.magic/run_lvs]: s8sram16x16_corner/2 = 1 | -[verify.magic/run_lvs]: s8sram16x16_corner/3 = 1 | -[verify.magic/run_lvs]: s8sram16x16_cornera/1 = 1 | -[verify.magic/run_lvs]: s8sram16x16_cornera/3 = 1 | -[verify.magic/run_lvs]: s8sram16x16_cornerb/2 = 1 | -[verify.magic/run_lvs]: s8sram16x16_cornerb/3 = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /dummy_array_0/a_1674_61# |Net: br_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /dummy_array_0/a_1174_61# |Net: br_0_1 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /dummy_array_0/a_674_61# |Net: br_0_2 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /dummy_array_0/a_38_62# |Net: br_0_3 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/wl0 = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_0/ |Net: vpwr -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/vpwr = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_1/ |Net: vgnd -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/vgnd = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/vgnd = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_2/ |Net: rbl_bl_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/bl0 = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/bl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_3/ |Net: rbl_br_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/bl1 = 3 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/bl1 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_4/ |Net: rbl_wl0_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/wl0 = 1 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 4 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_5/ |Net: rbl_wl1_0_0 -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1/wl1 = 1 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 4 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_6/ |Net: dummy_arraydummy_row_0/vdd -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/vgnd = 4 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_7/ |Net: /bitcell_array/col_0_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/bl0 = 2 -[verify.magic/run_lvs]: | s8sram_cell_opt1/bl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1421# |Net: /bitcell_array/col_1_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/bl0 = 2 -[verify.magic/run_lvs]: | s8sram_cell_opt1/bl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /replica_column_0/a_38_789# |Net: /bitcell_array/col_2_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_62# = 1 | s8sram_cell_opt1a/bl0 = 2 -[verify.magic/run_lvs]: | s8sram_cell_opt1/bl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /dummy_array_0/a_1538_220# |Net: /bitcell_array/col_3_bitcell -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | s8sram_cell_opt1a/bl0 = 2 -[verify.magic/run_lvs]: | s8sram_cell_opt1/bl0 = 2 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /dummy_array_0/a_1038_220# |Net: /bitcell_array/vdd -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | s8sram_cell_opt1a/vgnd = 8 -[verify.magic/run_lvs]: | s8sram_cell_opt1/vgnd = 8 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /dummy_array_0/a_538_220# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /dummy_array_0/a_38_220# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_0/ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_1/ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_2/ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_3/ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_4/ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_5/ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_6/ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1a_7/ |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1579# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /replica_column_0/a_38_947# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_0/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_1/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_2/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_3/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_4/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_5/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_6/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_7/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1737# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1105# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /replica_column_0/a_38_473# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_62# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_0/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_1/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_2/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_3/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_4/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_5/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_6/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /bitcell_array_0/s8sram_cell_opt1_7/s |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1895# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /replica_column_0/a_38_1263# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: /replica_column_0/a_38_631# |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/a_38_220# = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_3 -[verify.magic/run_lvs]: | s8sram_cell_opt1/vpwr = 4 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_1 -[verify.magic/run_lvs]: | s8sram_cell_opt1/vpwr = 4 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 1 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_3 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 4 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_1 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl1 = 4 -[verify.magic/run_lvs]: | s8sram_cell_opt1/wl0 = 1 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_2 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 4 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching net) |Net: wl1_0_0 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/vpwr = 4 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 1 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_2 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 4 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl0 = 1 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching net) |Net: wl0_0_0 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl1 = 4 -[verify.magic/run_lvs]: | s8sram_cell_opt1a/wl0 = 1 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: wl1_0_1 |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 5 | -[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 5 | -[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: wl1_0_3 |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1/wl1 = 5 | -[verify.magic/run_lvs]: s8sram_cell_opt1/wl0 = 5 | -[verify.magic/run_lvs]: s8sram_cell_opt1/s8sram_cell_met2_0/m2_0 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Net: wl1_0_0 |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 5 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 5 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Net: wl1_0_2 |(no matching net) -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl1 = 5 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/wl0 = 5 | -[verify.magic/run_lvs]: s8sram_cell_opt1a/s8sram_cell_met2_0/m2_ | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: DEVICE mismatches: Class fragments follow (with node fanout counts): -[verify.magic/run_lvs]: Circuit 1: replica_bitcell_array |Circuit 2: replica_bitcell_array -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: s8_col_cap_array_0//s8sram16x16_ |(no matching instance) -[verify.magic/run_lvs]: (drain,source) = (12,12) | -[verify.magic/run_lvs]: gate = 40 | -[verify.magic/run_lvs]: bulk = 30 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8_col_cap_array_0//s8sram16x16_ |(no matching instance) -[verify.magic/run_lvs]: (drain,source) = (12,12) | -[verify.magic/run_lvs]: gate = 40 | -[verify.magic/run_lvs]: bulk = 30 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8_col_cap_array_0//s8sram16x16_ |(no matching instance) -[verify.magic/run_lvs]: (drain,source) = (12,12) | -[verify.magic/run_lvs]: gate = 40 | -[verify.magic/run_lvs]: bulk = 30 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8_col_cap_array_0//s8sram16x16_ |(no matching instance) -[verify.magic/run_lvs]: (drain,source) = (12,12) | -[verify.magic/run_lvs]: gate = 40 | -[verify.magic/run_lvs]: bulk = 30 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: replica_column_0//s8sram16x16_co |(no matching instance) -[verify.magic/run_lvs]: (drain,source) = (12,12) | -[verify.magic/run_lvs]: gate = 40 | -[verify.magic/run_lvs]: bulk = 30 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8_col_cap_array_0//s8sram16x16_ |(no matching instance) -[verify.magic/run_lvs]: 1 = 76 | -[verify.magic/run_lvs]: 2 = 40 | -[verify.magic/run_lvs]: 3 = 40 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram_wlstrap_0 |(no matching instance) -[verify.magic/run_lvs]: 1 = 76 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram16x16_wlstr |(no matching instance) -[verify.magic/run_lvs]: 1 = 76 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: replica_column_0//s8sram16x16_co |(no matching instance) -[verify.magic/run_lvs]: 1 = 76 | -[verify.magic/run_lvs]: 2 = 40 | -[verify.magic/run_lvs]: 3 = 40 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8_row_cap_array_0//s8sram16x16_ |(no matching instance) -[verify.magic/run_lvs]: 1 = 76 | -[verify.magic/run_lvs]: 2 = 40 | -[verify.magic/run_lvs]: 3 = 40 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8_row_cap_array_0//s8sram16x16_ |(no matching instance) -[verify.magic/run_lvs]: 1 = 40 | -[verify.magic/run_lvs]: 2 = 76 | -[verify.magic/run_lvs]: 3 = 40 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8_row_cap_array_0//s8sram16x16_ |(no matching instance) -[verify.magic/run_lvs]: 1 = 76 | -[verify.magic/run_lvs]: 2 = 76 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8_row_cap_array_0//s8sram16x16_ |(no matching instance) -[verify.magic/run_lvs]: 1 = 76 | -[verify.magic/run_lvs]: 2 = 76 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: s8_row_cap_array_0_0//s8sram16x1 |(no matching instance) -[verify.magic/run_lvs]: 1 = 76 | -[verify.magic/run_lvs]: 2 = 40 | -[verify.magic/run_lvs]: 3 = 40 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: replica_column_0//s8sram_cell_op |Instance: replica_columnreplica_col_0/s8sr -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 5 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 76 | vgnd = 5 -[verify.magic/run_lvs]: wl0 = 76 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 76 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: replica_column_0//s8sram_cell_op |Instance: bitcell_array/s8sram_cell_opt1ro -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: replica_column_0//s8sram_cell_op |Instance: bitcell_array/s8sram_cell_opt1ro -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ro -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |(no matching instance) -[verify.magic/run_lvs]: bl0 = 12 | -[verify.magic/run_lvs]: bl1 = 12 | -[verify.magic/run_lvs]: vgnd = 76 | -[verify.magic/run_lvs]: vpwr = 76 | -[verify.magic/run_lvs]: vpb = 40 | -[verify.magic/run_lvs]: wl1 = 15 | -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |(no matching instance) -[verify.magic/run_lvs]: bl0 = 12 | -[verify.magic/run_lvs]: bl1 = 12 | -[verify.magic/run_lvs]: vgnd = 76 | -[verify.magic/run_lvs]: vpwr = 76 | -[verify.magic/run_lvs]: vpb = 40 | -[verify.magic/run_lvs]: wl1 = 15 | -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching instance) |Instance: replica_columnreplica_col_0/s8sr -[verify.magic/run_lvs]: | bl0 = 5 -[verify.magic/run_lvs]: | bl1 = 5 -[verify.magic/run_lvs]: | wl0 = 5 -[verify.magic/run_lvs]: | wl1 = 5 -[verify.magic/run_lvs]: | vpwr = 5 -[verify.magic/run_lvs]: | vgnd = 5 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching instance) |Instance: replica_columnreplica_col_0/s8sr -[verify.magic/run_lvs]: | bl0 = 5 -[verify.magic/run_lvs]: | bl1 = 5 -[verify.magic/run_lvs]: | wl0 = 5 -[verify.magic/run_lvs]: | wl1 = 5 -[verify.magic/run_lvs]: | vpwr = 5 -[verify.magic/run_lvs]: | vgnd = 5 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Instance: replica_column_0//s8sram_cell_op |Instance: dummy_arraydummy_row_0/s8sram_ce -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 1 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 4 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: replica_column_0//s8sram_cell_op |Instance: dummy_arraydummy_row_0/s8sram_ce -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 1 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 4 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: dummy_arraydummy_row_0/s8sram_ce -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 1 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 4 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: dummy_arraydummy_row_0/s8sram_ce -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 1 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 4 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: bitcell_array_0//s8sram_cell_opt |Instance: bitcell_array/s8sram_cell_opt1ar -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 15 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 15 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 15 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram_cell_opt1a |Instance: bitcell_array/s8sram_cell_opt1ar -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 76 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 76 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 76 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram_cell_opt1a |Instance: bitcell_array/s8sram_cell_opt1ar -[verify.magic/run_lvs]: bl0 = 12 | bl0 = 4 -[verify.magic/run_lvs]: bl1 = 12 | bl1 = 5 -[verify.magic/run_lvs]: vgnd = 76 | wl0 = 5 -[verify.magic/run_lvs]: vpwr = 76 | wl1 = 5 -[verify.magic/run_lvs]: vpb = 40 | vpwr = 5 -[verify.magic/run_lvs]: wl1 = 76 | vgnd = 16 -[verify.magic/run_lvs]: wl0 = 76 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 76 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram_cell_opt1a |(no matching instance) -[verify.magic/run_lvs]: bl0 = 12 | -[verify.magic/run_lvs]: bl1 = 12 | -[verify.magic/run_lvs]: vgnd = 76 | -[verify.magic/run_lvs]: vpwr = 76 | -[verify.magic/run_lvs]: vpb = 40 | -[verify.magic/run_lvs]: wl1 = 76 | -[verify.magic/run_lvs]: wl0 = 76 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 76 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: Instance: dummy_array_0//s8sram_cell_opt1a |(no matching instance) -[verify.magic/run_lvs]: bl0 = 12 | -[verify.magic/run_lvs]: bl1 = 12 | -[verify.magic/run_lvs]: vgnd = 76 | -[verify.magic/run_lvs]: vpwr = 76 | -[verify.magic/run_lvs]: vpb = 40 | -[verify.magic/run_lvs]: wl1 = 76 | -[verify.magic/run_lvs]: wl0 = 76 | -[verify.magic/run_lvs]: vnb = 30 | -[verify.magic/run_lvs]: a_38_62# = 1 | -[verify.magic/run_lvs]: s8sram_cell_met2_0/m2_0_59# = 76 | -[verify.magic/run_lvs]: a_38_220# = 1 | -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: (no matching instance) |Instance: replica_columnreplica_col_0/s8sr -[verify.magic/run_lvs]: | bl0 = 5 -[verify.magic/run_lvs]: | bl1 = 5 -[verify.magic/run_lvs]: | wl0 = 5 -[verify.magic/run_lvs]: | wl1 = 5 -[verify.magic/run_lvs]: | vpwr = 5 -[verify.magic/run_lvs]: | vgnd = 5 -[verify.magic/run_lvs]: | -[verify.magic/run_lvs]: (no matching instance) |Instance: replica_columnreplica_col_0/s8sr -[verify.magic/run_lvs]: | bl0 = 5 -[verify.magic/run_lvs]: | bl1 = 5 -[verify.magic/run_lvs]: | wl0 = 5 -[verify.magic/run_lvs]: | wl1 = 5 -[verify.magic/run_lvs]: | vpwr = 5 -[verify.magic/run_lvs]: | vgnd = 5 -[verify.magic/run_lvs]: --------------------------------------------------------------------------------------- -[verify.magic/run_lvs]: Netlists do not match. -[verify.magic/run_lvs]: Netlists do not match. ERROR: file magic.py: line 285: replica_bitcell_array LVS mismatch (results in /home/jesse/output/replica_bitcell_array.lvs.report) diff --git a/missing_pin.gds b/missing_pin.gds index 0bad623f..692677d9 100644 Binary files a/missing_pin.gds and b/missing_pin.gds differ diff --git a/sram_0.05/sram_16_16_sky130_0.05.log b/sram_0.05/sram_16_16_sky130_0.05.log index 8ca4e621..e8814676 100644 --- a/sram_0.05/sram_16_16_sky130_0.05.log +++ b/sram_0.05/sram_16_16_sky130_0.05.log @@ -6,13 +6,15 @@ [globals/import_tech]: Importing technology: sky130 [globals/import_tech]: Adding technology path: /home/jesse/openram/technology [globals/init_paths]: Creating temp directory: /home/jesse/output/ -[verify/]: Initializing verify... -[verify/]: LVS/DRC/PEX disabled. [characterizer/]: Initializing characterizer... [characterizer/]: Finding spice simulator. +[verify/]: Initializing verify... +[verify/]: LVS/DRC/PEX disabled. +WARNING: file __init__.py: line 79: Did not find Magic. + [globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r |==============================================================================| -|========= OpenRAM v1.1.5 =========| +|========= OpenRAM v1.1.6 =========| |========= =========| |========= VLSI Design and Automation Lab =========| |========= Computer Science and Engineering Department =========| @@ -23,7 +25,7 @@ |========= Temp dir: /home/jesse/output/ =========| |========= See LICENSE for license info =========| |==============================================================================| -** Start: 07/01/2020 04:43:37 +** Start: 10/07/2020 13:40:02 Technology: sky130 Total size: 256 bits Word size: 16 @@ -42,6 +44,7 @@ Performing simulation-based characterization with ngspice [sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4 Words per row: 1 Output files are: +/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.lvs /home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.sp /home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.v /home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.lib @@ -55,198 +58,11 @@ Output files are: [dff_array/__init__]: Creating data_dff rows=1 cols=16 [dff_array/__init__]: Creating wmask_dff rows=1 cols=2 [bank/__init__]: create sram of size 16 with 16 words -[port_data/__init__]: create data port of size 16 with 1 words per row -[precharge/__init__]: creating precharge cell precharge -[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55 -[pgate/bin_width]: binning pmos tx, target: 0.55, found 0.55 x 1 = 0.55 -[precharge_array/__init__]: Creating precharge_array -[precharge/__init__]: creating precharge cell precharge_0 -[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55 -[sense_amp_array/__init__]: Creating sense_amp_array -[sense_amp/__init__]: Create sense_amp -[write_driver_array/__init__]: Creating write_driver_array -[write_driver/__init__]: Create write_driver -[write_mask_and_array/__init__]: Creating write_mask_and_array -[pand2/__init__]: Creating pand2 pand2 -[pnand2/__init__]: creating pnand2 structure pnand2 with size of 1 -[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74 -[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12 -[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74 -[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74 -[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.12 x 1 = 1.12 -[pdriver/__init__]: creating pdriver pdriver -[pinv/__init__]: creating pinv structure pinv with size of 2.0 -[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36 -[pgate/bin_width]: binning pmos tx, target: 0.36, found 0.42 x 1 = 0.42 -[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74 -[pinv/determine_tx_mults]: pinv bin count: 2 pinv bin error: 0.06481481481481488 percent error 0.03240740740740744 -[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74 -[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.12 x 1 = 1.12 -[port_data/__init__]: create data port of size 16 with 1 words per row -[precharge_array/__init__]: Creating precharge_array_0 -[precharge/__init__]: creating precharge cell precharge_1 -[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55 [port_address/__init__]: create data port of cols 16 rows 16 [and2_dec/__init__]: Creating and2_dec and2_dec [pinv_dec/__init__]: creating pinv_dec structure pinv_dec with size of 1 [pinv/__init__]: creating pinv structure pinv_dec with size of 1 -[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36 -[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12 -[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36 -[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.12 x 1 = 1.12 +[pgate/best_bin]: binning nmos tx, target: 0.36, found 1 x 0.36 = 0.36 +[pgate/best_bin]: binning pmos tx, target: 1.12, found 1 x 1.12 = 1.12 [and3_dec/__init__]: Creating and3_dec and3_dec -[wordline_driver_array/__init__]: Creating wordline_driver_array -[wordline_driver/__init__]: Creating wordline_driver wordline_driver -[pinv_dec/__init__]: creating pinv_dec structure pinv_dec_0 with size of 16 -[pinv/__init__]: creating pinv structure pinv_dec_0 with size of 16 -[pgate/bin_width]: binning nmos tx, target: 5.76, found 7.0 x 1 = 7.0 -[pgate/bin_width]: binning pmos tx, target: 17.28, found 7.0 x 3 = 21.0 -[pgate/bin_width]: binning nmos tx, target: 7.0, found 7.0 x 1 = 7.0 -[pgate/bin_width]: binning pmos tx, target: 7.0, found 7.0 x 1 = 7.0 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array 16 x 16 -[bitcell_base_array/__init__]: Creating bitcell_array 16 x 16 -[replica_bitcell_1rw_1r/__init__]: Create replica bitcell 1rw+1r object -[dummy_bitcell_1rw_1r/__init__]: Create dummy bitcell 1rw+1r object -[col_cap_bitcell_1rw_1r/__init__]: Create col_cap bitcell 1rw+1r object -[bitcell_base_array/__init__]: Creating dummy_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array 20 x 1 -[row_cap_bitcell_1rw_1r/__init__]: Create row_cap bitcell 1rw+1r object -[bitcell_base_array/__init__]: Creating row_cap_array_0 20 x 1 -[control_logic/__init__]: Creating control_logic_rw -[dff_buf/__init__]: Creating dff_buf -[pinv/__init__]: creating pinv structure pinv_0 with size of 2 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74 -[pinv/determine_tx_mults]: pinv bin count: 4 pinv bin error: 0.12962962962962976 percent error 0.03240740740740744 -[pinv/__init__]: creating pinv structure pinv_1 with size of 4 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68 -[pinv/determine_tx_mults]: pinv bin count: 6 pinv bin error: 0.44212962962962954 percent error 0.07368827160493825 -[pgate/bin_width]: binning nmos tx, target: 1.68, found 1.68 x 1 = 1.68 -[pgate/bin_width]: binning pmos tx, target: 1.6499999999999997, found 1.65 x 1 = 1.65 -[dff_buf_array/__init__]: Creating dff_buf_array -[dff_buf/__init__]: Creating dff_buf_0 -[pand2/__init__]: Creating pand2 pand2_0 -[pnand2/__init__]: creating pnand2 structure pnand2_0 with size of 1 -[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74 -[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12 -[pdriver/__init__]: creating pdriver pdriver_0 -[pinv/__init__]: creating pinv structure pinv_2 with size of 12 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04 -[pinv/determine_tx_mults]: pinv bin count: 8 pinv bin error: 0.6890432098765432 percent error 0.0861304012345679 -[pgate/bin_width]: binning nmos tx, target: 1.68, found 1.68 x 1 = 1.68 -[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0 -[pbuf/__init__]: creating pbuf with size of 16 -[pinv/__init__]: creating pinv structure pinv_3 with size of 16 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0 -[pinv/determine_tx_mults]: pinv bin count: 10 pinv bin error: 0.7723765432098766 percent error 0.07723765432098766 -[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0 -[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0 -[pdriver/__init__]: creating pdriver pdriver_1 -[pinv/__init__]: creating pinv structure pinv_4 with size of 1 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36 -[pinv/determine_tx_mults]: pinv bin count: 12 pinv bin error: 0.8094135802469137 percent error 0.0674511316872428 -[pinv/__init__]: creating pinv structure pinv_5 with size of 1 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36 -[pinv/determine_tx_mults]: pinv bin count: 14 pinv bin error: 0.8464506172839508 percent error 0.06046075837742505 -[pinv/__init__]: creating pinv structure pinv_6 with size of 4 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68 -[pinv/determine_tx_mults]: pinv bin count: 16 pinv bin error: 1.1589506172839505 percent error 0.07243441358024691 -[pinv/__init__]: creating pinv structure pinv_7 with size of 13 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 14.04, found 2.0 x 8 = 16.0 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.68, found 1.68 x 3 = 5.04 -[pinv/determine_tx_mults]: pinv bin count: 18 pinv bin error: 1.3754748338081673 percent error 0.07641526854489818 -[pgate/bin_width]: binning nmos tx, target: 1.68, found 1.68 x 1 = 1.68 -[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0 -[pinv/__init__]: creating pinv structure pinv_8 with size of 38 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 41.04, found 2.0 x 21 = 42.0 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.68, found 2.0 x 7 = 14.0 -[pinv/determine_tx_mults]: pinv bin count: 20 pinv bin error: 1.4222584595391614 percent error 0.07111292297695807 -[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0 -[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0 -[pdriver/__init__]: creating pdriver pdriver_2 -[pinv/__init__]: creating pinv structure pinv_9 with size of 2 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74 -[pinv/determine_tx_mults]: pinv bin count: 22 pinv bin error: 1.4870732743539763 percent error 0.06759423974336255 -[pinv/__init__]: creating pinv structure pinv_10 with size of 5 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 5.3999999999999995, found 2.0 x 3 = 6.0 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.7999999999999998, found 2.0 x 1 = 2.0 -[pinv/determine_tx_mults]: pinv bin count: 24 pinv bin error: 1.7092954965761986 percent error 0.07122064569067495 -[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0 -[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0 -[pand3/__init__]: Creating pand3 pand3 -[pnand3/__init__]: creating pnand3 structure pnand3 with size of 1 -[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74 -[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12 -[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74 -[pdriver/__init__]: creating pdriver pdriver_3 -[pinv/__init__]: creating pinv structure pinv_11 with size of 24 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 25.919999999999998, found 2.0 x 13 = 26.0 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 8.64, found 2.0 x 5 = 10.0 -[pinv/determine_tx_mults]: pinv bin count: 26 pinv bin error: 1.8697893237366925 percent error 0.07191497398987279 -[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0 -[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0 -[pand3/__init__]: Creating pand3 pand3_0 -[pdriver/__init__]: creating pdriver pdriver_4 -[pinv/__init__]: creating pinv structure pinv_12 with size of 16 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0 -[pinv/determine_tx_mults]: pinv bin count: 28 pinv bin error: 1.9531226570700257 percent error 0.06975438060964377 -[pinv/__init__]: creating pinv structure pinv_13 with size of 1 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36 -[pinv/determine_tx_mults]: pinv bin count: 30 pinv bin error: 1.9901596941070627 percent error 0.06633865647023543 -[pnand2/__init__]: creating pnand2 structure pnand2_1 with size of 1 -[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74 -[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12 -[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4] -[pinv/__init__]: creating pinv structure pinv_14 with size of 1 -[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36 -[pinv/determine_tx_mults]: pinv bin count: 32 pinv bin error: 2.0271967311441 percent error 0.06334989784825312 -[control_logic/__init__]: Creating control_logic_r -[dff_buf_array/__init__]: Creating dff_buf_array_0 -[pdriver/__init__]: creating pdriver pdriver_5 -[pinv/__init__]: creating pinv structure pinv_15 with size of 12 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04 -[pinv/determine_tx_mults]: pinv bin count: 34 pinv bin error: 2.2741103113910133 percent error 0.06688559739385333 -[pinv/__init__]: creating pinv structure pinv_16 with size of 37 -[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350 -[pinv/determine_tx_mults]: prebinning pmos tx, target: 39.96, found 2.0 x 20 = 40.0 -[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.32, found 2.0 x 7 = 14.0 -[pinv/determine_tx_mults]: pinv bin count: 36 pinv bin error: 2.3261623634430655 percent error 0.06461562120675182 -[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0 -[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0 -** Submodules: 8.6 seconds -** Placement: 0.0 seconds -*** Init supply router: 56.2 seconds -[supply_hannan_router/route]: Running hannan supply router on vdd and gnd... -[supply_hannan_router/retrieve_pins]: Retrieving pins for vdd. -[supply_hannan_router/retrieve_pins]: Retrieving pins for gnd. -[supply_hannan_router/route]: Building matrix +[and4_dec/__init__]: Creating and4_dec and4_dec diff --git a/sram_1b_16_1rw_sky130.log b/sram_1b_16_1rw_sky130.log index 9b298b1e..f57734de 100644 --- a/sram_1b_16_1rw_sky130.log +++ b/sram_1b_16_1rw_sky130.log @@ -13,6 +13,7 @@ [globals/get_tool]: Using PEX: /usr/local/bin/magic [globals/get_tool]: Using GDS: /usr/local/bin/magic [bitcell_base_array/__init__]: Creating replica_bitcell_array 4 x 4 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array 4 x 4 +[replica_bitcell_array/__init__]: Creating replica_bitcell_array 4 x 4 rbls: [1, 0] left_rbl: None right_rbl: None [bitcell_base_array/__init__]: Creating bitcell_array 4 x 4 -[bitcell_base_array/__init__]: Creating dummy_array 1 x 4 +[bitcell_array/__init__]: Creating bitcell_array 4 x 4 +[bitcell_base_array/__init__]: Creating replica_column 7 x 1