no wl for col end

2026-08-30 01:48:33 +02:00 · 2020-10-08 03:34:16 -07:00
parent 4a1a7e637e
commit d40c3588ed
15 changed files with 99 additions and 2076 deletions
@@ -98,7 +98,7 @@ class dummy_array(bitcell_base_array):
                              height=self.height)
        
        wl_names = self.cell.get_all_wl_names()
-        if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
+        if not props.compare_ports(props.bitcell.split_wl):
            for row in range(self.row_size):
                for port in self.all_ports:
                    wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])