mirror of https://github.com/VLSIDA/OpenRAM.git
52 lines
2.2 KiB
Python
52 lines
2.2 KiB
Python
# This is a temp file. Remove either this or the fake_sram.py
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from modules import sram
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import debug
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from globals import OPTS
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import os
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class fake_sram_v2(sram):
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def create_netlist(self):
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# Make sure spice file is here
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debug.check(os.path.exists(self.sp_name), "Spice netlist in {} not found".format(self.sp_name))
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def generate_pins(self):
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self.pins = ['vdd', 'gnd']
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self.pins.extend(['clk{}'.format(port) for port in range(
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OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports)])
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for port in range(OPTS.num_rw_ports):
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self.pins.extend(['din{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['dout{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]'.format(port, bit)
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for bit in range(self.addr_size)])
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#if self.num_wmasks != 0:
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# self.pins.extend(['wmask{0}[{1}]'.format(port, bit)
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# for bit in range(self.num_wmasks)])
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self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
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start_port = OPTS.num_rw_ports
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for port in range(start_port, start_port + OPTS.num_r_ports):
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self.pins.extend(['dout{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]'.format(port, bit)
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for bit in range(self.addr_size)])
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self.pins.extend(['csb{}'.format(port)])
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start_port += OPTS.num_r_ports
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for port in range(start_port, start_port + OPTS.num_w_ports):
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self.pins.extend(['din{0}[{1}]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]'.format(port, bit)
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for bit in range(self.addr_size)])
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if self.num_wmasks != 0:
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self.pins.extend(['wmask{0}[{1}]'.format(port, bit)
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for bit in range(self.num_wmasks)])
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self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
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