mirror of https://github.com/VLSIDA/OpenRAM.git
302 lines
9.5 KiB
Python
302 lines
9.5 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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class cell:
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def __init__(self, port_order, port_types, port_map=None, body_bias=None, hard_cell=True, boundary_layer="boundary"):
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# Some cells may have body bias (well taps) exposed as ports
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self._body_bias = body_bias
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# Specifies if this is a hard (i.e. GDS) cell
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self._hard_cell = hard_cell
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self._boundary_layer = boundary_layer
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# Specifies the port directions
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self._port_types_map = {x: y for (x, y) in zip(port_order, port_types)}
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# Specifies a map from OpenRAM names to cell names
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# by default it is 1:1
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if not port_map:
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self._port_map = {x: x for x in port_order}
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else:
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self._port_map = port_map
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# Update mapping of names
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self._original_port_order = port_order
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self._port_order = port_order
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# Create an index array
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self._port_indices = [self._port_order.index(x) for x in self._original_port_order]
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# Update ordered name list
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self._port_names = [self._port_map[x] for x in self._port_order]
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# Update ordered type list
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self._port_types = [self._port_types_map[x] for x in self._port_order]
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@property
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def hard_cell(self):
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return self._hard_cell
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@property
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def port_names(self):
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return self._port_names
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@property
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def port_order(self):
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return self._port_order
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@port_order.setter
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def port_order(self, port_order):
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# If we are going to redefine more ports (i.e. well biases) don't init stuff
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old_port_len = len(self._port_order)
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if old_port_len == len(port_order):
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self._port_order = port_order
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# Update ordered name list in the new order
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self._port_names = [self._port_map[x] for x in self._port_order]
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# Update ordered type list in the new order
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self._port_types = [self._port_types_map[x] for x in self._port_order]
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# Update the index array
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self._port_indices = [self._port_order.index(x) for x in self._original_port_order]
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else:
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# Do the default constructor again except for types stuff which hasn't been set yet
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self._port_order = port_order
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self._original_port_order = self._port_order
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self._port_map = {x: x for x in self._port_order}
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self._port_indices = [self._port_order.index(x) for x in self._original_port_order]
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self._port_names = [self._port_map[x] for x in self._port_order]
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@property
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def port_indices(self):
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return self._port_indices
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@property
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def port_map(self):
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return self._port_map
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@port_map.setter
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def port_map(self, port_map):
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self._port_map = port_map
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# Update ordered name list to use the new names
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self._port_names = [self._port_map[x] for x in self._port_order]
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@property
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def body_bias(self):
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return self._body_bias
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@body_bias.setter
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def body_bias(self, body_bias):
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# It is assumed it is [nwell, pwell]
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self._body_bias = body_bias
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self._port_map['vnb'] = body_bias[0]
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self._port_types['vnb'] = "GROUND"
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self._port_map['vpb'] = body_bias[1]
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self._port_types['vpb'] = "POWER"
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@property
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def port_types(self):
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return self._port_types
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@port_types.setter
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def port_types(self, port_types):
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self._port_types = port_types
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# Specifies the port directions
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self._port_types_map = {x: y for (x, y) in zip(self._port_order, self._port_types)}
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# Update ordered type list
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self._port_types = [self._port_types_map[x] for x in self._port_order]
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@property
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def boundary_layer(self):
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return self._boundary_layer
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@boundary_layer.setter
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def boundary_layer(self, x):
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self._boundary_layer = x
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class _pins:
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def __init__(self, pin_dict):
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# make the pins elements of the class to allow "." access.
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# For example: props.bitcell.cell_1port.pin.bl = "foobar"
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for k, v in pin_dict.items():
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self.__dict__[k] = v
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class _mirror_axis:
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def __init__(self, x, y):
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self.x = x
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self.y = y
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class _ptx:
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def __init__(self, model_is_subckt, bin_spice_models):
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self.model_is_subckt = model_is_subckt
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self.bin_spice_models = bin_spice_models
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class _pgate:
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def __init__(self, add_implants):
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self.add_implants = add_implants
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class bitcell(cell):
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def __init__(self, port_order, port_types, port_map=None, storage_nets=["Q", "Q_bar"], mirror=None, end_caps=False):
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super().__init__(port_order, port_types, port_map)
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self.end_caps = end_caps
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if not mirror:
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self.mirror = _mirror_axis(True, False)
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else:
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self.mirror = mirror
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self.storage_nets = storage_nets
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self.wl_layer = "m1"
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self.wl_dir = "H"
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self.bl_layer = "m2"
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self.bl_dir = "V"
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self.vdd_layer = "m1"
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self.vdd_dir = "H"
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self.gnd_layer = "m1"
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self.gnd_dir = "H"
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class cell_properties():
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"""
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This contains meta information about the custom designed cells. For
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instance, pin names, or the axis on which they need to be mirrored. These
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can be overriden in the tech.py file.
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"""
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def __init__(self):
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self.names = {}
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self.names["bitcell_1port"] = "cell_1rw"
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self.names["bitcell_2port"] = "cell_2rw"
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self.names["dummy_bitcell_1port"] = "dummy_cell_1rw"
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self.names["dummy_bitcell_2port"] = "dummy_cell_2rw"
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self.names["replica_bitcell_1port"] = "replica_cell_1rw"
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self.names["replica_bitcell_2port"] = "replica_cell_2rw"
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self.names["col_cap_bitcell_1port"] = "col_cap_cell_1rw"
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self.names["col_cap_bitcell_2port"] = "col_cap_cell_2rw"
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self.names["row_cap_bitcell_1port"] = "row_cap_cell_1rw"
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self.names["row_cap_bitcell_2port"] = "row_cap_cell_2rw"
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self.names["internal"] = "internal"
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self.use_strap = False
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self._ptx = _ptx(model_is_subckt=False,
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bin_spice_models=False)
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self._pgate = _pgate(add_implants=False)
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self._inv_dec = cell(["A", "Z", "vdd", "gnd"],
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["INPUT", "OUTPUT", "POWER", "GROUND"])
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self._nand2_dec = cell(["A", "B", "Z", "vdd", "gnd"],
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["INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"])
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self._nand3_dec = cell(["A", "B", "C", "Z", "vdd", "gnd"],
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["INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"])
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self._nand4_dec = cell(["A", "B", "C", "D", "Z", "vdd", "gnd"],
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["INPUT", "INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"])
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self._dff = cell(["D", "Q", "clk", "vdd", "gnd"],
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["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
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self._write_driver = cell(['din', 'bl', 'br', 'en', 'vdd', 'gnd'],
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["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
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self._sense_amp = cell(['bl', 'br', 'dout', 'en', 'vdd', 'gnd'],
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["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
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self._bitcell_1port = bitcell(["bl", "br", "wl", "vdd", "gnd"],
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["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
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self._bitcell_2port = bitcell(["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"],
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["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"])
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self._col_cap_1port = bitcell(["bl", "br", "vdd"],
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["OUTPUT", "OUTPUT", "POWER"])
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self._row_cap_1port = bitcell(["wl", "gnd"],
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["INPUT", "POWER", "GROUND"])
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self._col_cap_2port = bitcell(["bl0", "br0", "bl1", "br1", "vdd"],
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["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "POWER"])
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self._row_cap_2port = bitcell(["wl0", "wl1", "gnd"],
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["INPUT", "INPUT", "POWER", "GROUND"])
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self._internal = cell([],[])
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@property
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def internal(self):
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return self._internal
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@property
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def ptx(self):
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return self._ptx
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@property
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def pgate(self):
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return self._pgate
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@property
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def inv_dec(self):
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return self._inv_dec
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@property
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def nand2_dec(self):
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return self._nand2_dec
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@property
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def nand3_dec(self):
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return self._nand3_dec
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@property
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def nand4_dec(self):
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return self._nand4_dec
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@property
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def dff(self):
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return self._dff
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@property
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def write_driver(self):
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return self._write_driver
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@property
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def sense_amp(self):
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return self._sense_amp
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@property
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def bitcell_1port(self):
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return self._bitcell_1port
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@property
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def bitcell_2port(self):
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return self._bitcell_2port
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@property
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def col_cap_1port(self):
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return self._col_cap_1port
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@property
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def row_cap_1port(self):
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return self._row_cap_1port
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@property
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def col_cap_2port(self):
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return self._col_cap_2port
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@property
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def row_cap_2port(self):
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return self._row_cap_2port
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