mirror of https://github.com/VLSIDA/OpenRAM.git
120 lines
4.9 KiB
Python
120 lines
4.9 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import math
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from openram import debug
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from openram import tech
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from openram import OPTS
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from .simulation import simulation
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class cacti(simulation):
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"""
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Delay model for the SRAM which which
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"""
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def __init__(self, sram, spfile, corner):
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super().__init__(sram, spfile, corner)
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# self.targ_read_ports = []
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# self.targ_write_ports = []
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# self.period = 0
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# if self.write_size != self.word_size:
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# self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
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# else:
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# self.num_wmasks = 0
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#self.set_load_slew(0, 0)
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self.set_corner(corner)
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self.create_signal_names()
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self.add_graph_exclusions()
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self.set_params()
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def set_params(self):
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"""Set parameters specific to the corner being simulated"""
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self.params = {}
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# Set the specific functions to use for timing defined in the SRAM module
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self.params["model_name"] = OPTS.model_name
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# Only parameter right now is r_on which is dependent on Vdd
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self.params["r_nch_on"] = self.vdd_voltage / tech.spice["i_on_n"]
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self.params["r_pch_on"] = self.vdd_voltage / tech.spice["i_on_p"]
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def get_lib_values(self, load_slews):
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"""
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Return the analytical model results for the SRAM.
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"""
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if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0:
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debug.warning("In analytical mode, all ports have the timing of the first read port.")
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# Probe set to 0th bit, does not matter for analytical delay.
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self.set_probe('0' * self.bank_addr_size, 0)
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self.create_graph()
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self.set_internal_spice_names()
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self.create_measurement_names()
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port = self.read_ports[0]
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, self.probe_data))
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# Select the path with the bitline (bl)
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bl_name, br_name = self.get_bl_name(self.graph.all_paths, port)
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bl_path = [path for path in self.graph.all_paths if bl_name in path][0]
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# Set delay/power for slews and loads
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port_data = self.get_empty_measure_data_dict()
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power = self.analytical_power(load_slews)
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debug.info(1, 'Slew (ns), Load (fF), Delay(ns), Slew(ns)')
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max_delay = 0.0
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for load,slew in load_slews:
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# Calculate delay based on slew and load
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# Calculations expect Farad, input is Femto-Farad
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load_farad = load*1e-15
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#load_farad = 0.052275e-12
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slew = 0
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path_delays = self.graph.get_timing(bl_path, self.corner, slew, load_farad, self.params)
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total_delay = self.sum_delays(path_delays)
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delay_ns = total_delay.delay/1e-9
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slew_ns = total_delay.slew/1e-9
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max_delay = max(max_delay, total_delay.delay)
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debug.info(1,'{}, {}, {}, {}'.format(slew,
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load,
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delay_ns,
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slew_ns))
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# Delay is only calculated on a single port and replicated for now.
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for port in self.all_ports:
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for mname in self.delay_meas_names + self.power_meas_names:
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if "power" in mname:
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port_data[port][mname].append(power.dynamic)
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elif "delay" in mname and port in self.read_ports:
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port_data[port][mname].append(total_delay.delay / 1e-9)
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elif "slew" in mname and port in self.read_ports:
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port_data[port][mname].append(total_delay.slew / 1e-9)
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# Margin for error in period. Calculated by averaging required margin for a small and large
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# memory. FIXME: margin is quite large, should be looked into.
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period_margin = 1.85
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sram_data = {"min_period": (max_delay / 1e-9) * 2 * period_margin,
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"leakage_power": power.leakage}
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debug.info(2, "SRAM Data:\n{}".format(sram_data))
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debug.info(2, "Port Data:\n{}".format(port_data))
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return (sram_data, port_data)
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def analytical_power(self, load_slews):
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"""Get the dynamic and leakage power from the SRAM"""
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# slews unused, only last load is used
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load = load_slews[-1][0]
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power = self.sram.analytical_power(self.corner, load)
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# convert from nW to mW
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power.dynamic /= 1e6
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power.leakage /= 1e6
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debug.info(1, "Dynamic Power: {0} mW".format(power.dynamic))
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debug.info(1, "Leakage Power: {0} mW".format(power.leakage))
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return power
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