mirror of https://github.com/VLSIDA/OpenRAM.git
Merge remote-tracking branch 'private/dev' into dev
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commit
8a2fa90cd5
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@ -185,9 +185,8 @@ class delay(simulation):
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self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9)
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self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9)
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self.sen_meas.meta_str = sram_op.READ_ZERO
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self.sen_meas.meta_str = sram_op.READ_ZERO
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self.sen_meas.meta_add_delay = True
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self.sen_meas.meta_add_delay = True
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self.dout_volt_meas.append(self.sen_meas)
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return self.dout_volt_meas + [self.sen_meas]
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return self.dout_volt_meas
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def create_read_bit_measures(self):
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def create_read_bit_measures(self):
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""" Adds bit measurements for read0 and read1 cycles """
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""" Adds bit measurements for read0 and read1 cycles """
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@ -1351,7 +1350,7 @@ class delay(simulation):
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Return the analytical model results for the SRAM.
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Return the analytical model results for the SRAM.
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"""
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"""
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if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0:
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if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0:
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debug.warning("Analytical characterization results are not supported for multiport.")
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debug.warning("Analytical characterization for multiple read ports may be inaccurate.")
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# Probe set to 0th bit, does not matter for analytical delay.
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# Probe set to 0th bit, does not matter for analytical delay.
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self.set_probe('0'*self.addr_size, 0)
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self.set_probe('0'*self.addr_size, 0)
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