diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index b7faaec3..afb9c7f6 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -185,9 +185,8 @@ class delay(simulation):
         self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9)
         self.sen_meas.meta_str = sram_op.READ_ZERO        
         self.sen_meas.meta_add_delay = True
-        self.dout_volt_meas.append(self.sen_meas)
-        
-        return self.dout_volt_meas
+
+        return self.dout_volt_meas + [self.sen_meas]
      
     def create_read_bit_measures(self):
         """ Adds bit measurements for read0 and read1 cycles """
@@ -1351,7 +1350,7 @@ class delay(simulation):
         Return the analytical model results for the SRAM. 
         """
         if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0:
-            debug.warning("Analytical characterization results are not supported for multiport.")
+            debug.warning("Analytical characterization for multiple read ports may be inaccurate.")
         
         # Probe set to 0th bit, does not matter for analytical delay.
         self.set_probe('0'*self.addr_size, 0)