mirror of https://github.com/VLSIDA/OpenRAM.git
merging changes in bitcell.py
This commit is contained in:
Michael Timothy Grimes
commit
7f46a0dead
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@ -120,3 +120,10 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
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for i in self.insts:
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text+=str(i)+",\n"
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return text
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def analytical_power(self, proc, vdd, temp, load):
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""" Get total power of a module """
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total_module_power = self.return_power()
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for inst in self.insts:
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total_module_power += inst.mod.analytical_power(proc, vdd, temp, load)
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return total_module_power
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@ -121,7 +121,8 @@ class layout(lef.lef):
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def add_inst(self, name, mod, offset=[0,0], mirror="R0",rotate=0):
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"""Adds an instance of a mod to this module"""
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self.insts.append(geometry.instance(name, mod, offset, mirror, rotate))
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debug.info(4, "adding instance" + ",".join(x.name for x in self.insts))
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debug.info(3, "adding instance {}".format(self.insts[-1]))
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debug.info(4, "instance list: " + ",".join(x.name for x in self.insts))
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return self.insts[-1]
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def get_inst(self, name):
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@ -453,6 +454,7 @@ class layout(lef.lef):
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def gds_write_file(self, newLayout):
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"""Recursive GDS write function"""
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# Visited means that we already prepared self.gds for this subtree
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if self.visited:
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return
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for i in self.insts:
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@ -468,10 +470,11 @@ class layout(lef.lef):
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"""Write the entire gds of the object to the file."""
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debug.info(3, "Writing to {0}".format(gds_name))
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#self.gds = gdsMill.VlsiLayout(name=self.name,units=GDS["unit"])
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writer = gdsMill.Gds2writer(self.gds)
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# clear the visited flag for the traversal
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self.clear_visited()
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# MRG: 3/2/18 We don't want to clear the visited flag since
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# this would result in duplicates of all instances being placed in self.gds
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# which may have been previously processed!
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#self.clear_visited()
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# recursively create all the remaining objects
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self.gds_write_file(self.gds)
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# populates the xyTree data structure for gds
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@ -97,8 +97,8 @@ class spice(verilog.verilog):
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for i in range(len(self.spice)):
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self.spice[i] = self.spice[i].rstrip(" \n")
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# find first subckt line in the file
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subckt = re.compile("^.subckt", re.IGNORECASE)
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# find the correct subckt line in the file
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subckt = re.compile("^.subckt {}".format(self.name), re.IGNORECASE)
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subckt_line = filter(subckt.search, self.spice)[0]
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# parses line into ports and remove subckt
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self.pins = subckt_line.split(" ")[2:]
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@ -214,6 +214,9 @@ class spice(verilog.verilog):
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def generate_rc_net(self,lump_num, wire_length, wire_width):
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return wire_spice_model(lump_num, wire_length, wire_width)
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def return_power(self, dynamic=0.0, leakage=0.0):
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return power_data(dynamic, leakage)
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class delay_data:
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"""
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@ -246,6 +249,37 @@ class delay_data:
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assert isinstance(other,delay_data)
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return delay_data(other.delay + self.delay,
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self.slew)
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class power_data:
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"""
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This is the power class to represent the power information
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Dynamic and leakage power are stored as a single object with this class.
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"""
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def __init__(self, dynamic=0.0, leakage=0.0):
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""" init function support two init method"""
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# will take single input as a coordinate
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self.dynamic = dynamic
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self.leakage = leakage
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def __str__(self):
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""" override print function output """
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return "Power Data: Dynamic "+str(self.dynamic)+", Leakage "+str(self.leakage)+" in nW"
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def __add__(self, other):
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"""
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Override - function (left), for power_data: a+b != b+a
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"""
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assert isinstance(other,power_data)
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return power_data(other.dynamic + self.dynamic,
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other.leakage + self.leakage)
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def __radd__(self, other):
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"""
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Override - function (left), for power_data: a+b != b+a
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"""
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assert isinstance(other,power_data)
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return power_data(other.dynamic + self.dynamic,
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other.leakage + self.leakage)
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class wire_spice_model:
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@ -721,17 +721,24 @@ class delay():
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delay_hl.append(bank_delay.delay/1e3)
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slew_lh.append(bank_delay.slew/1e3)
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slew_hl.append(bank_delay.slew/1e3)
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power = sram.analytical_power(self.process, self.vdd_voltage, self.temperature, load)
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#convert from nW to mW
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power.dynamic /= 1e6
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power.leakage /= 1e6
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debug.info(1,"Dynamic Power: {0} mW".format(power.dynamic))
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debug.info(1,"Leakage Power: {0} mW".format(power.leakage))
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data = {"min_period": 0,
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"delay_lh": delay_lh,
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"delay_hl": delay_hl,
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"slew_lh": slew_lh,
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"slew_hl": slew_hl,
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"read0_power": 0,
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"read1_power": 0,
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"write0_power": 0,
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"write1_power": 0,
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"leakage_power": 0
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"read0_power": power.dynamic,
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"read1_power": power.dynamic,
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"write0_power": power.dynamic,
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"write1_power": power.dynamic,
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"leakage_power": power.leakage
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}
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return data
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@ -1228,3 +1228,4 @@ class bank(design.design):
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result = msf_addr_delay + decoder_delay + word_driver_delay \
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+ bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay
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return result
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@ -34,7 +34,8 @@ class bitcell(design.design):
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c_para = spice["min_tx_drain_c"]
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result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew, swing = swing)
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return result
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def list_bitcell_pins(self, col, row):
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# Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array
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bitcell_pins = ["bl[{0}]".format(col),
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@ -56,4 +57,12 @@ class bitcell(design.design):
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column_pins = ["BL", "BR"]
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return column_pins
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def analytical_power(self, proc, vdd, temp, load):
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"""Bitcell power in nW. Only characterizes leakage."""
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from tech import spice
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leakage = spice["bitcell_leakage"]
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dynamic = 0 #temporary
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total_power = self.return_power(dynamic, leakage)
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return total_power
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@ -179,6 +179,25 @@ class bitcell_array(design.design):
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#we do not consider the delay over the wire for now
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return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
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wl_to_cell_delay.slew)
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def analytical_power(self, proc, vdd, temp, load):
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"""Power of Bitcell array and bitline in nW."""
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from tech import drc
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# Dynamic Power from Bitline
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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bl_swing = 0.1 #This should probably be defined in the tech file or input
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freq = spice["default_event_rate"]
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bitline_dynamic = bl_swing*cell_load*vdd*vdd*freq #not sure if calculation is correct
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#Calculate the bitcell power which currently only includes leakage
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cell_power = self.cell.analytical_power(proc, vdd, temp, load)
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#Leakage power grows with entire array and bitlines.
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total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
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cell_power.leakage * self.column_size * self.row_size)
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return total_power
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def gen_wl_wire(self):
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wl_wire = self.generate_rc_net(int(self.column_size), self.width, drc["minwidth_metal1"])
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@ -98,7 +98,7 @@ class control_logic(design.design):
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# GAP between main control and replica bitline
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self.replica_bitline_gap = 2*self.m2_pitch
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def add_modules(self):
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@ -688,4 +688,4 @@ class control_logic(design.design):
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height=pin.height(),
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width=pin.width())
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@ -494,6 +494,7 @@ class hierarchical_decoder(design.design):
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result = result + z_t_decodeout_delay
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return result
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def input_load(self):
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if self.determine_predecodes(self.num_inputs)[1]==0:
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pre = self.pre2_4
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@ -55,5 +55,6 @@ class hierarchical_predecode2x4(hierarchical_predecode):
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return a_t_b_delay + b_t_z_delay + a_t_out_delay
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def input_load(self):
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return self.nand.input_load()
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@ -64,6 +64,5 @@ class hierarchical_predecode3x8(hierarchical_predecode):
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return a_t_b_delay + b_t_z_delay + a_t_out_delay
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def input_load(self):
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return self.nand.input_load()
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@ -26,4 +26,25 @@ class ms_flop(design.design):
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from tech import spice
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result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"])
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return result
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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from tech import spice
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c_eff = self.calculate_effective_capacitance(load)
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f = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*f
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power_leak = spice["msflop_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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from tech import spice, parameter
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c_load = load
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c_para = spice["flop_para_cap"]#ff
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transistion_prob = spice["flop_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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@ -134,3 +134,4 @@ class ms_flop_array(design.design):
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def analytical_delay(self, slew, load=0.0):
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return self.ms.analytical_delay(slew=slew, load=load)
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@ -30,3 +30,8 @@ class sense_amp(design.design):
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result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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return self.return_delay(result.delay, result.slew)
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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#Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
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total_power = self.return_power()
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return total_power
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@ -117,3 +117,4 @@ class sense_amp_array(design.design):
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def analytical_delay(self, slew, load=0.0):
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return self.amp.analytical_delay(slew=slew, load=load)
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@ -32,7 +32,12 @@ class tri_gate(design.design):
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r = spice["min_tx_r"]
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c_para = spice["min_tx_drain_c"]
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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#Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
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total_power = self.return_power()
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return total_power
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def input_load(self):
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return 9*spice["min_tx_gate_c"]
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@ -111,3 +111,4 @@ class tri_gate_array(design.design):
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def analytical_delay(self, slew, load=0.0):
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return self.tri.analytical_delay(slew = slew, load = load)
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@ -205,6 +205,7 @@ class wordline_driver(design.design):
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net_t_wl = self.inv.analytical_delay(decode_t_net.slew, load)
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return decode_t_net + net_t_wl
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def input_load(self):
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return self.nand2.input_load()
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@ -241,3 +241,20 @@ class pinv(pgate.pgate):
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r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"])
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*freq
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power_leak = spice["inv_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transistion_prob = spice["inv_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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@ -213,3 +213,20 @@ class pnand2(pgate.pgate):
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r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"])
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*freq
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power_leak = spice["nand2_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transistion_prob = spice["nand2_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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@ -233,3 +233,20 @@ class pnand3(pgate.pgate):
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r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"])
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*freq
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power_leak = spice["nand3_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transistion_prob = spice["nand3_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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@ -223,3 +223,21 @@ class pnor2(pgate.pgate):
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r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"])
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*freq
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power_leak = spice["nor2_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transistion_prob = spice["nor2_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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@ -1015,7 +1015,6 @@ class sram(design.design):
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""" LH and HL are the same in analytical model. """
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return self.bank.analytical_delay(slew,load)
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||||
|
||||
def save_output(self):
|
||||
""" Save all the output files while reporting time to do it as well. """
|
||||
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@ cell (sram_2_16_1_freepdk45){
|
|||
|
||||
leakage_power () {
|
||||
when : "CSb";
|
||||
value : 0;
|
||||
value : 0.000173;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DATA){
|
||||
|
|
@ -298,19 +298,19 @@ cell (sram_2_16_1_freepdk45){
|
|||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
rise_power(scalar){
|
||||
values("0.0");
|
||||
values("0.065526962224");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0");
|
||||
values("0.065526962224");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
rise_power(scalar){
|
||||
values("0.0");
|
||||
values("0.065526962224");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0");
|
||||
values("0.065526962224");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@ cell (sram_2_16_1_scn3me_subm){
|
|||
|
||||
leakage_power () {
|
||||
when : "CSb";
|
||||
value : 0;
|
||||
value : 0.000173;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DATA){
|
||||
|
|
@ -298,19 +298,19 @@ cell (sram_2_16_1_scn3me_subm){
|
|||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
rise_power(scalar){
|
||||
values("0.0");
|
||||
values("10.9314668117");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0");
|
||||
values("10.9314668117");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
rise_power(scalar){
|
||||
values("0.0");
|
||||
values("10.9314668117");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0");
|
||||
values("10.9314668117");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
|
|
|
|||
|
|
@ -113,19 +113,8 @@ def write_netgen_script(cell_name, sp_name):
|
|||
f = open(run_file, "w")
|
||||
f.write("#!/bin/sh\n")
|
||||
f.write("{} -noconsole << EOF\n".format(OPTS.lvs_exe[1]))
|
||||
f.write("readnet spice {}.spice\n".format(cell_name))
|
||||
f.write("readnet spice {}\n".format(sp_name))
|
||||
f.write("ignore class c\n")
|
||||
f.write("permute transistors\n")
|
||||
f.write("equate class {{{0}.spice nfet}} {{{1} n}}\n".format(cell_name, sp_name))
|
||||
f.write("equate class {{{0}.spice pfet}} {{{1} p}}\n".format(cell_name, sp_name))
|
||||
# This circuit has symmetries and needs to be flattened to resolve them or the banks won't pass
|
||||
# Is there a more elegant way to add this when needed?
|
||||
f.write("flatten class {{{0}.spice precharge_array}}\n".format(cell_name))
|
||||
f.write("property {{{0}.spice nfet}} remove as ad ps pd\n".format(cell_name))
|
||||
f.write("property {{{0}.spice pfet}} remove as ad ps pd\n".format(cell_name))
|
||||
f.write("property {{{0} n}} remove as ad ps pd\n".format(sp_name))
|
||||
f.write("property {{{0} p}} remove as ad ps pd\n".format(sp_name))
|
||||
f.write("readnet spice {0}.spice\n".format(cell_name))
|
||||
f.write("readnet spice {0}\n".format(sp_name))
|
||||
# Allow some flexibility in W size because magic will snap to a lambda grid
|
||||
# This can also cause disconnects unfortunately!
|
||||
# f.write("property {{{0}{1}.spice nfet}} tolerance {{w 0.1}}\n".format(OPTS.openram_temp,
|
||||
|
|
@ -137,6 +126,24 @@ def write_netgen_script(cell_name, sp_name):
|
|||
f.write("EOF\n")
|
||||
f.close()
|
||||
os.system("chmod u+x {}".format(run_file))
|
||||
|
||||
setup_file = OPTS.openram_temp + "setup.tcl"
|
||||
f = open(setup_file, "w")
|
||||
f.write("ignore class c\n")
|
||||
f.write("equate class {{nfet {0}.spice}} {{n {1}}}\n".format(cell_name, sp_name))
|
||||
f.write("equate class {{pfet {0}.spice}} {{p {1}}}\n".format(cell_name, sp_name))
|
||||
# This circuit has symmetries and needs to be flattened to resolve them or the banks won't pass
|
||||
# Is there a more elegant way to add this when needed?
|
||||
f.write("flatten class {{{0}.spice precharge_array}}\n".format(cell_name))
|
||||
f.write("property {{nfet {0}.spice}} remove as ad ps pd\n".format(cell_name))
|
||||
f.write("property {{pfet {0}.spice}} remove as ad ps pd\n".format(cell_name))
|
||||
f.write("property {{n {0}}} remove as ad ps pd\n".format(sp_name))
|
||||
f.write("property {{p {0}}} remove as ad ps pd\n".format(sp_name))
|
||||
f.write("permute transistors\n")
|
||||
f.write("permute pins n source drain\n")
|
||||
f.write("permute pins p source drain\n")
|
||||
f.close()
|
||||
|
||||
|
||||
def run_drc(cell_name, gds_name, extract=False):
|
||||
"""Run DRC check on a cell which is implemented in gds_name."""
|
||||
|
|
|
|||
|
|
@ -1,10 +1,5 @@
|
|||
*master-slave flip-flop with both output and inverted ouput
|
||||
|
||||
.SUBCKT ms_flop din dout dout_bar clk vdd gnd
|
||||
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
|
||||
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
|
||||
.ENDS flop
|
||||
|
||||
.SUBCKT dlatch din dout dout_bar clk clk_bar vdd gnd
|
||||
*clk inverter
|
||||
mPff1 clk_bar clk vdd vdd PMOS_VTG W=180.0n L=50n m=1
|
||||
|
|
@ -27,3 +22,8 @@ mtmP2 int1 clk_bar dout vdd PMOS_VTG W=180.0n L=50n m=1
|
|||
mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1
|
||||
.ENDS dlatch
|
||||
|
||||
.SUBCKT ms_flop din dout dout_bar clk vdd gnd
|
||||
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
|
||||
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
|
||||
.ENDS flop
|
||||
|
||||
|
|
|
|||
|
|
@ -283,6 +283,21 @@ spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
|||
spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["dff_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
|
||||
# analytical power parameters, many values are temporary
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
|
||||
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
|
||||
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
|
||||
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
|
||||
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
|
||||
spice["msflop_leakage"] = 1 # Leakage power of flop in nW
|
||||
spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF
|
||||
|
||||
spice["default_event_rate"] = 100 # Default event activity of every gate. MHz
|
||||
spice["flop_transisition_prob"] = .5 # Transition probability of inverter.
|
||||
spice["inv_transisition_prob"] = .5 # Transition probability of inverter.
|
||||
spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand.
|
||||
spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand.
|
||||
spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor.
|
||||
|
||||
###################################################
|
||||
##END Spice Simulation Parameters
|
||||
|
|
|
|||
|
|
@ -0,0 +1,176 @@
|
|||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction,
|
||||
and distribution as defined by Sections 1 through 9 of this document.
|
||||
|
||||
"Licensor" shall mean the copyright owner or entity authorized by
|
||||
the copyright owner that is granting the License.
|
||||
|
||||
"Legal Entity" shall mean the union of the acting entity and all
|
||||
other entities that control, are controlled by, or are under common
|
||||
control with that entity. For the purposes of this definition,
|
||||
"control" means (i) the power, direct or indirect, to cause the
|
||||
direction or management of such entity, whether by contract or
|
||||
otherwise, or (ii) ownership of fifty percent (50%) or more of the
|
||||
outstanding shares, or (iii) beneficial ownership of such entity.
|
||||
|
||||
"You" (or "Your") shall mean an individual or Legal Entity
|
||||
exercising permissions granted by this License.
|
||||
|
||||
"Source" form shall mean the preferred form for making modifications,
|
||||
including but not limited to software source code, documentation
|
||||
source, and configuration files.
|
||||
|
||||
"Object" form shall mean any form resulting from mechanical
|
||||
transformation or translation of a Source form, including but
|
||||
not limited to compiled object code, generated documentation,
|
||||
and conversions to other media types.
|
||||
|
||||
"Work" shall mean the work of authorship, whether in Source or
|
||||
Object form, made available under the License, as indicated by a
|
||||
copyright notice that is included in or attached to the work
|
||||
(an example is provided in the Appendix below).
|
||||
|
||||
"Derivative Works" shall mean any work, whether in Source or Object
|
||||
form, that is based on (or derived from) the Work and for which the
|
||||
editorial revisions, annotations, elaborations, or other modifications
|
||||
represent, as a whole, an original work of authorship. For the purposes
|
||||
of this License, Derivative Works shall not include works that remain
|
||||
separable from, or merely link (or bind by name) to the interfaces of,
|
||||
the Work and Derivative Works thereof.
|
||||
|
||||
"Contribution" shall mean any work of authorship, including
|
||||
the original version of the Work and any modifications or additions
|
||||
to that Work or Derivative Works thereof, that is intentionally
|
||||
submitted to Licensor for inclusion in the Work by the copyright owner
|
||||
or by an individual or Legal Entity authorized to submit on behalf of
|
||||
the copyright owner. For the purposes of this definition, "submitted"
|
||||
means any form of electronic, verbal, or written communication sent
|
||||
to the Licensor or its representatives, including but not limited to
|
||||
communication on electronic mailing lists, source code control systems,
|
||||
and issue tracking systems that are managed by, or on behalf of, the
|
||||
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|
||||
excluding communication that is conspicuously marked or otherwise
|
||||
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|
||||
|
||||
"Contributor" shall mean Licensor and any individual or Legal Entity
|
||||
on behalf of whom a Contribution has been received by Licensor and
|
||||
subsequently incorporated within the Work.
|
||||
|
||||
2. Grant of Copyright License. Subject to the terms and conditions of
|
||||
this License, each Contributor hereby grants to You a perpetual,
|
||||
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
|
||||
copyright license to reproduce, prepare Derivative Works of,
|
||||
publicly display, publicly perform, sublicense, and distribute the
|
||||
Work and such Derivative Works in Source or Object form.
|
||||
|
||||
3. Grant of Patent License. Subject to the terms and conditions of
|
||||
this License, each Contributor hereby grants to You a perpetual,
|
||||
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
|
||||
(except as stated in this section) patent license to make, have made,
|
||||
use, offer to sell, sell, import, and otherwise transfer the Work,
|
||||
where such license applies only to those patent claims licensable
|
||||
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|
||||
Contribution(s) alone or by combination of their Contribution(s)
|
||||
with the Work to which such Contribution(s) was submitted. If You
|
||||
institute patent litigation against any entity (including a
|
||||
cross-claim or counterclaim in a lawsuit) alleging that the Work
|
||||
or a Contribution incorporated within the Work constitutes direct
|
||||
or contributory patent infringement, then any patent licenses
|
||||
granted to You under this License for that Work shall terminate
|
||||
as of the date such litigation is filed.
|
||||
|
||||
4. Redistribution. You may reproduce and distribute copies of the
|
||||
Work or Derivative Works thereof in any medium, with or without
|
||||
modifications, and in Source or Object form, provided that You
|
||||
meet the following conditions:
|
||||
|
||||
(a) You must give any other recipients of the Work or
|
||||
Derivative Works a copy of this License; and
|
||||
|
||||
(b) You must cause any modified files to carry prominent notices
|
||||
stating that You changed the files; and
|
||||
|
||||
(c) You must retain, in the Source form of any Derivative Works
|
||||
that You distribute, all copyright, patent, trademark, and
|
||||
attribution notices from the Source form of the Work,
|
||||
excluding those notices that do not pertain to any part of
|
||||
the Derivative Works; and
|
||||
|
||||
(d) If the Work includes a "NOTICE" text file as part of its
|
||||
distribution, then any Derivative Works that You distribute must
|
||||
include a readable copy of the attribution notices contained
|
||||
within such NOTICE file, excluding those notices that do not
|
||||
pertain to any part of the Derivative Works, in at least one
|
||||
of the following places: within a NOTICE text file distributed
|
||||
as part of the Derivative Works; within the Source form or
|
||||
documentation, if provided along with the Derivative Works; or,
|
||||
within a display generated by the Derivative Works, if and
|
||||
wherever such third-party notices normally appear. The contents
|
||||
of the NOTICE file are for informational purposes only and
|
||||
do not modify the License. You may add Your own attribution
|
||||
notices within Derivative Works that You distribute, alongside
|
||||
or as an addendum to the NOTICE text from the Work, provided
|
||||
that such additional attribution notices cannot be construed
|
||||
as modifying the License.
|
||||
|
||||
You may add Your own copyright statement to Your modifications and
|
||||
may provide additional or different license terms and conditions
|
||||
for use, reproduction, or distribution of Your modifications, or
|
||||
for any such Derivative Works as a whole, provided Your use,
|
||||
reproduction, and distribution of the Work otherwise complies with
|
||||
the conditions stated in this License.
|
||||
|
||||
5. Submission of Contributions. Unless You explicitly state otherwise,
|
||||
any Contribution intentionally submitted for inclusion in the Work
|
||||
by You to the Licensor shall be under the terms and conditions of
|
||||
this License, without any additional terms or conditions.
|
||||
Notwithstanding the above, nothing herein shall supersede or modify
|
||||
the terms of any separate license agreement you may have executed
|
||||
with Licensor regarding such Contributions.
|
||||
|
||||
6. Trademarks. This License does not grant permission to use the trade
|
||||
names, trademarks, service marks, or product names of the Licensor,
|
||||
except as required for reasonable and customary use in describing the
|
||||
origin of the Work and reproducing the content of the NOTICE file.
|
||||
|
||||
7. Disclaimer of Warranty. Unless required by applicable law or
|
||||
agreed to in writing, Licensor provides the Work (and each
|
||||
Contributor provides its Contributions) on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||
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|
||||
of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
|
||||
PARTICULAR PURPOSE. You are solely responsible for determining the
|
||||
appropriateness of using or redistributing the Work and assume any
|
||||
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|
||||
|
||||
8. Limitation of Liability. In no event and under no legal theory,
|
||||
whether in tort (including negligence), contract, or otherwise,
|
||||
unless required by applicable law (such as deliberate and grossly
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
9. Accepting Warranty or Additional Liability. While redistributing
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
incurred by, or claims asserted against, such Contributor by reason
|
||||
of your accepting any such warranty or additional liability.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,47 @@
|
|||
These technology files are from the FreePDK45nm design kit.
|
||||
|
||||
FreePDK 45nm verion 1.4 (2011-04-07)
|
||||
(Subversion Repository revision 173)
|
||||
|
||||
Copyright 2007 - W. Rhett Davis, Paul Franzon, Michael Bucher,
|
||||
and Sunil Basavarajaiah, North Carolina State University
|
||||
Copyright 2008 - W. Rhett Davis, Michael Bucher, and Sunil Basavarajaiah,
|
||||
North Carolina State University (ncsu_basekit subtree)
|
||||
James Stine, and Ivan Castellanos,
|
||||
and Oklahoma State University (osu_soc subtree)
|
||||
Copyright 2011 - W. Rhett Davis, and Harun Demircioglu,
|
||||
North Carolina State University
|
||||
|
||||
SVRF Technology in this kit is licensed under the the agreement found
|
||||
in the file SVRF_EULA_06Feb09.txt in this directory. All other files
|
||||
are licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use these files except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
***** Welcome to the FreePDK 45nm Free, Open-Source Process Design Kit *****
|
||||
|
||||
This initiative is brought to you by the Semiconductor Research
|
||||
Corporation (SRC), the National Science Foundation (NSF), Silicon
|
||||
Integration Initiative (Si2), Mentor Graphics, and Synopsys.
|
||||
|
||||
This version of the kit was created by Rhett Davis, Paul Franzon,
|
||||
Michael Bucher, Sunil Basavarajaiah, and Harun Demircioglu
|
||||
of North Carolina State University, and James Stine and Ivan Castellanos
|
||||
of Oklahoma State University.
|
||||
|
||||
Contributions and modifications to this kit are welcomed and encouraged.
|
||||
|
||||
***** Contents *****
|
||||
|
||||
ncsu_basekit/ Base kit for custom design
|
||||
osu_soc/ Standard-cell kit for synthesis, place, & route
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,7 @@
|
|||
import os
|
||||
CWD = os.environ.get("OPENRAM_TECH") + "/freepdk45/tf"
|
||||
ui().importCds("default", CWD+"/display.drf", CWD+"/FreePDK45.tf", 1000, 1, CWD+"/layers.map")
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
active drawing 1 0
|
||||
pwell drawing 2 0
|
||||
nwell drawing 3 0
|
||||
nimplant drawing 4 0
|
||||
pimplant drawing 5 0
|
||||
vtg drawing 6 0
|
||||
vth drawing 7 0
|
||||
thkox drawing 8 0
|
||||
poly drawing 9 0
|
||||
contact drawing 10 0
|
||||
metal1 drawing 11 0
|
||||
via1 drawing 12 0
|
||||
metal2 drawing 13 0
|
||||
via2 drawing 14 0
|
||||
metal3 drawing 15 0
|
||||
via3 drawing 16 0
|
||||
metal4 drawing 17 0
|
||||
via4 drawing 18 0
|
||||
metal5 drawing 19 0
|
||||
via5 drawing 20 0
|
||||
metal6 drawing 21 0
|
||||
via6 drawing 22 0
|
||||
metal7 drawing 23 0
|
||||
via7 drawing 24 0
|
||||
metal8 drawing 25 0
|
||||
via8 drawing 26 0
|
||||
metal9 drawing 27 0
|
||||
via9 drawing 28 0
|
||||
metal10 drawing 29 0
|
||||
text drawing 239 0
|
||||
|
|
@ -5,6 +5,6 @@
|
|||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL n NMOS (LEVEL=49 VTHO=0.669845 KP=113.7771E-6
|
||||
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
|
||||
+ NSUB=6E16 U0=461 K1=0.5705 TOX=13.9n VERSION=3.3.0)
|
||||
|
||||
|
|
|
|||
|
|
@ -5,5 +5,5 @@
|
|||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 KP=366.0244-6
|
||||
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
|
||||
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)
|
||||
|
|
|
|||
|
|
@ -5,5 +5,5 @@
|
|||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL n NMOS (LEVEL=49 VTHO=0.669845 KP=113.7771E-6
|
||||
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
|
||||
+ NSUB=6E16 U0=458 K1=0.5705 TOX=13.9n VERSION=3.3.0)
|
||||
|
|
|
|||
|
|
@ -5,5 +5,5 @@
|
|||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 KP=366.0244-6
|
||||
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
|
||||
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)
|
||||
|
|
|
|||
|
|
@ -5,6 +5,6 @@
|
|||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL n NMOS (LEVEL=49 VTHO=0.669845 KP=113.7771E-6
|
||||
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
|
||||
+ NSUB=6E16 U0=460 K1=0.5705 TOX=13.9n VERSION=3.3.0)
|
||||
|
||||
|
|
|
|||
|
|
@ -5,5 +5,5 @@
|
|||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 KP=366.0244-6
|
||||
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
|
||||
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)
|
||||
|
|
|
|||
|
|
@ -1,10 +1,5 @@
|
|||
*master-slave flip-flop with both output and inverted ouput
|
||||
|
||||
.subckt ms_flop din dout dout_bar clk vdd gnd
|
||||
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
|
||||
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
|
||||
.ends flop
|
||||
|
||||
.subckt dlatch din dout dout_bar clk clk_bar vdd gnd
|
||||
*clk inverter
|
||||
mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1
|
||||
|
|
@ -27,3 +22,8 @@ mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1
|
|||
mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1
|
||||
.ends dlatch
|
||||
|
||||
.subckt ms_flop din dout dout_bar clk vdd gnd
|
||||
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
|
||||
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
|
||||
.ends flop
|
||||
|
||||
|
|
|
|||
|
|
@ -246,7 +246,21 @@ spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
|||
spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
|
||||
# analytical power parameters, many values are temporary
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
|
||||
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
|
||||
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
|
||||
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
|
||||
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
|
||||
spice["msflop_leakage"] = 1 # Leakage power of flop in nW
|
||||
spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF
|
||||
|
||||
spice["default_event_rate"] = 100 # Default event activity of every gate. MHz
|
||||
spice["flop_transisition_prob"] = .5 # Transition probability of inverter.
|
||||
spice["inv_transisition_prob"] = .5 # Transition probability of inverter.
|
||||
spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand.
|
||||
spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand.
|
||||
spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor.
|
||||
###################################################
|
||||
##END Spice Simulation Parameters
|
||||
###################################################
|
||||
|
|
|
|||
|
|
@ -0,0 +1,4 @@
|
|||
The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004,
|
||||
2006. Users are free to use or modify the NCSU CDK as appropriate as long
|
||||
as this notice appears in the modified package. The NCSU CDK is
|
||||
provided with NO WARRANTY.
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
;; NCSU CDK v. 1.6.0.beta
|
||||
;; Last Modified: 2007-07-12
|
||||
|
||||
The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004,
|
||||
2006, 2007. Users are free to use or modify the NCSU CDK as appropriate as long
|
||||
as this notice appears in the modified package. The NCSU CDK is
|
||||
provided with NO WARRANTY.
|
||||
|
||||
As of version 1.5.1, all documentation for the NCSU CDK is provided
|
||||
by the NCSU EDA Wiki which can be found at:
|
||||
|
||||
http://www.eda.ncsu.edu/
|
||||
|
||||
This beta release of the kit is to be used in migrating to Cadence Virtuoso 6.1
|
||||
for OpenAccess. Details of the conversion of the CDK from the CDB version can
|
||||
be found in the file cdb2oa/OA_Conversion.txt.
|
||||
|
||||
This kit is not yet fully supported. Please post problems and solutions at
|
||||
http://www.chiptalk.org -> Forums -> NCSU CDK -> NCSU CDK 1.6.0.beta for Virtuoso 6.1
|
||||
|
|
@ -0,0 +1,714 @@
|
|||
drDefineDisplay(
|
||||
;( DisplayName )
|
||||
( display )
|
||||
)
|
||||
drDefineColor(
|
||||
;( DisplayName ColorsName Red Green Blue )
|
||||
( display white 255 255 255 )
|
||||
( display yellow 255 255 0 )
|
||||
( display silver 217 230 255 )
|
||||
( display cream 255 255 204 )
|
||||
( display pink 255 191 242 )
|
||||
( display magenta 255 0 255 )
|
||||
( display lime 0 255 0 )
|
||||
( display tan 255 230 191 )
|
||||
( display cyan 0 255 255 )
|
||||
( display cadetBlue 57 191 255 )
|
||||
( display orange 255 128 0 )
|
||||
( display red 255 51 51 )
|
||||
( display purple 153 0 230 )
|
||||
( display green 0 204 102 )
|
||||
( display brown 191 64 38 )
|
||||
( display blue 51 77 255 )
|
||||
( display slate 140 140 166 )
|
||||
( display gold 217 204 0 )
|
||||
( display maroon 230 31 13 )
|
||||
( display violet 94 0 230 )
|
||||
( display forest 38 140 107 )
|
||||
( display chocolate 128 38 38 )
|
||||
( display navy 51 51 153 )
|
||||
( display black 0 0 0 )
|
||||
( display gray 204 204 217 )
|
||||
( display winColor1 166 166 166 )
|
||||
( display winColor2 115 115 115 )
|
||||
( display winColor3 189 204 204 )
|
||||
( display winColor4 204 204 204 )
|
||||
( display winColor5 199 199 199 )
|
||||
( display blinkRed 255 0 0 t )
|
||||
( display blinkYellow 255 255 0 t )
|
||||
( display blinkWhite 255 255 255 t )
|
||||
( display winBack 224 224 224 )
|
||||
( display winFore 128 0 0 )
|
||||
( display winText 51 51 51 )
|
||||
)
|
||||
drDefineStipple(
|
||||
;( DisplayName StippleName Bitmap )
|
||||
( display dots ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display dots1 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display hLine ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) )
|
||||
( display vLine ( ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) )
|
||||
( display cross ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) ) )
|
||||
( display grid ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) )
|
||||
( display slash ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) )
|
||||
( display backSlash ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) )
|
||||
( display hZigZag ( ( 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 )
|
||||
( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 )
|
||||
( 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 )
|
||||
( 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 )
|
||||
( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 )
|
||||
( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 )
|
||||
( 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 )
|
||||
( 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 )
|
||||
( 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 )
|
||||
( 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ) ) )
|
||||
( display vZigZag ( ( 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 )
|
||||
( 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 )
|
||||
( 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 )
|
||||
( 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 )
|
||||
( 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 )
|
||||
( 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 )
|
||||
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|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ) ) )
|
||||
( display dats5 ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
)
|
||||
drDefineLineStyle(
|
||||
;( DisplayName LineStyle Size Pattern )
|
||||
( display solid 1 (1 ) )
|
||||
( display dashed 1 (1 1 1 0 0 1 1 1 ) )
|
||||
( display dots 1 (1 0 0 ) )
|
||||
( display dashDot 1 (1 1 1 0 0 1 0 0 ) )
|
||||
( display shortDash 1 (1 1 0 0 ) )
|
||||
( display doubleDash 1 (1 1 1 1 0 0 1 1 0 0 ) )
|
||||
( display hidden 1 (1 0 0 0 ) )
|
||||
( display thickLine 3 (1 1 1 ) )
|
||||
( display lineStyle0 1 (1 ) )
|
||||
( display lineStyle1 1 (1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 ) )
|
||||
)
|
||||
drDefinePacket(
|
||||
;( DisplayName PacketName Stipple LineStyle Fill Outline [FillStyle])
|
||||
( display NwellNet dots4 thickLine slate slate outlineStipple)
|
||||
( display border stipple0 solid tan tan solid )
|
||||
( display y8 stipple0 solid gold gold solid )
|
||||
( display background stipple1 lineStyle0 black black outlineStipple)
|
||||
( display y9 stipple0 solid silver silver solid )
|
||||
( display Metal3Net dots4 solid navy navy outlineStipple)
|
||||
( display A1 stipple0 lineStyle0 winBack winBack solid )
|
||||
( display pin solid lineStyle0 red red solid )
|
||||
( display XPNet blank solid yellow yellow outline )
|
||||
( display hardFence stipple0 solid red red solid )
|
||||
( display PbaseNet dots4 solid yellow yellow outlineStipple)
|
||||
( display designFlow3 stipple1 lineStyle0 pink pink outlineStipple)
|
||||
( display A2 stipple0 lineStyle0 winBack winBack solid )
|
||||
( display Unrouted1 stipple0 lineStyle1 brown brown solid )
|
||||
( display RowLbl blank solid cyan cyan outline )
|
||||
( display edgeLayerPin stipple0 solid yellow yellow solid )
|
||||
( display instance blank solid winBack red outline )
|
||||
( display Nselect dots4 solid green green outlineStipple)
|
||||
( display snap stipple0 solid yellow yellow solid )
|
||||
( display pinAnt stipple0 solid red red solid )
|
||||
( display winAttentionText solid solid winText winText solid )
|
||||
( display designFlow2 stipple1 lineStyle0 purple purple outlineStipple)
|
||||
( display Unrouted2 stipple0 lineStyle1 red red solid )
|
||||
( display hilite blank solid white white outline )
|
||||
( display P2Con solid lineStyle0 orange orange solid )
|
||||
( display designFlow1 stipple1 lineStyle0 red red outlineStipple)
|
||||
( display grid1 stipple0 solid gray gray solid )
|
||||
( display Unrouted3 stipple0 lineStyle1 pink pink solid )
|
||||
( display ViaNet x solid magenta magenta outlineStipple)
|
||||
( display select stipple0 solid tan tan solid )
|
||||
( display Poly2Net dots4 lineStyle0 orange orange outlineStipple)
|
||||
( display winText solid solid winText winText solid )
|
||||
( display Unrouted4 stipple0 lineStyle1 orange orange solid )
|
||||
( display wireLbl solid lineStyle0 cyan cyan solid )
|
||||
( display designFlow7 stipple1 lineStyle0 cyan cyan outlineStipple)
|
||||
( display align stipple0 solid tan tan solid )
|
||||
( display Poly2Pin blank solid yellow yellow outline )
|
||||
( display Unrouted5 stipple0 lineStyle1 green green solid )
|
||||
( display unset stipple0 solid forest forest solid )
|
||||
( display Poly1Net dots4 lineStyle0 red red outlineStipple)
|
||||
( display Resistor dots2 lineStyle0 cyan cyan outlineStipple)
|
||||
( display DiodeNet dots4 lineStyle0 cream cream outlineStipple)
|
||||
( display designFlow6 stipple1 lineStyle0 tan tan outlineStipple)
|
||||
( display Unrouted6 stipple0 lineStyle1 blue blue solid )
|
||||
( display resist stipple0 solid cyan cyan solid )
|
||||
( display designFlow5 stipple1 lineStyle0 silver silver outlineStipple)
|
||||
( display CapWellNet brick solid slate slate outlineStipple)
|
||||
( display Unrouted7 stipple0 lineStyle1 purple purple solid )
|
||||
( display CannotoccupyBnd blank solid red red outline )
|
||||
( display winTopShadow solid solid white white solid )
|
||||
( display designFlow4 stipple1 lineStyle0 black black outlineStipple)
|
||||
( display softFence stipple0 solid yellow yellow solid )
|
||||
( display ResistorNet dots4 solid cyan cyan outlineStipple)
|
||||
( display winError solid solid winColor5 winColor5 solid )
|
||||
( display changedLayerTl1 stipple0 solid yellow yellow solid )
|
||||
( display prBoundaryLbl stipple0 solid purple purple solid )
|
||||
( display ActXNet x solid yellow yellow outlineStipple)
|
||||
( display Pbase stipple10 lineStyle0 yellow yellow outlineStipple)
|
||||
( display Active dots2 lineStyle0 yellow yellow outlineStipple)
|
||||
( display changedLayerTl0 stipple0 solid red red solid )
|
||||
( display spike stipple0 solid purple purple solid )
|
||||
( display Metal3 grid solid navy violet outlineStipple)
|
||||
( display text blank solid white white outline )
|
||||
( display Poly1Pin stipple0 lineStyle0 red red solid )
|
||||
( display Row blank solid cyan cyan outline )
|
||||
( display Pwell stipple9 lineStyle0 slate slate outlineStipple)
|
||||
( display Metal2 stipple5 lineStyle0 magenta magenta outlineStipple)
|
||||
( display wire solid lineStyle0 cyan cyan solid )
|
||||
( display ActX solid solid yellow yellow solid )
|
||||
( display Metal1 stipple6 lineStyle0 cadetBlue cadetBlue outlineStipple)
|
||||
( display Cannotoccupy blank solid red red outline )
|
||||
( display GroupLbl stipple0 solid green green solid )
|
||||
( display axis stipple0 solid slate slate solid )
|
||||
( display SiBlockNet x dashed tan tan outlineStipple)
|
||||
( display edgeLayer stipple0 solid gray gray solid )
|
||||
( display annotate2 stipple0 solid lime lime solid )
|
||||
( display Metal1Pin stipple0 lineStyle0 blue blue solid )
|
||||
( display Diode stipple7 lineStyle0 cream cream outlineStipple)
|
||||
( display Glass X lineStyle0 white white X )
|
||||
( display ViaXNet x solid magenta magenta outlineStipple)
|
||||
( display annotate3 stipple0 solid cyan cyan solid )
|
||||
( display Poly2 dots1 lineStyle0 orange orange outlineStipple)
|
||||
( display deviceAnt stipple0 solid yellow yellow solid )
|
||||
( display winBottomShadow solid solid winColor1 winColor1 solid )
|
||||
( display PselectNet dots4 solid brown brown outlineStipple)
|
||||
( display comment stipple0 lineStyle0 winBack winBack solid )
|
||||
( display Poly1 dots lineStyle0 red red outlineStipple)
|
||||
( display Unrouted stipple0 lineStyle1 winColor5 winColor5 solid )
|
||||
( display stretch stipple0 solid yellow yellow solid )
|
||||
( display XP blank lineStyle0 winBack gold outline )
|
||||
( display annotate1 stipple0 solid pink pink solid )
|
||||
( display Group stipple2 solid green green outlineStipple)
|
||||
( display deviceLbl stipple0 solid green green solid )
|
||||
( display annotate6 stipple0 solid silver silver solid )
|
||||
( display GlassNet blank solid yellow yellow outline )
|
||||
( display Canplace blank solid cyan cyan outline )
|
||||
( display annotate7 stipple0 solid red red solid )
|
||||
( display Via2 solid solid navy navy solid )
|
||||
( display Metal2Pin stipple0 lineStyle0 magenta magenta solid )
|
||||
( display annotate4 stipple0 solid yellow yellow solid )
|
||||
( display device1 stipple1 lineStyle0 green green outlineStipple)
|
||||
( display "90" blank solid white white outline )
|
||||
( display markerWarn x solid yellow yellow outlineStipple)
|
||||
( display text2 stipple1 lineStyle0 white white outlineStipple)
|
||||
( display CapacitorNet dots4 lineStyle0 tan tan outlineStipple)
|
||||
( display designFlow stipple1 lineStyle0 green green outlineStipple)
|
||||
( display hilite1 stipple0 solid silver silver solid )
|
||||
( display device blank solid green green outline )
|
||||
( display prBoundary stipple0 solid purple purple solid )
|
||||
( display annotate5 stipple0 solid white white solid )
|
||||
( display text1 stipple0 dashed white white solid )
|
||||
( display Via solid solid magenta magenta solid )
|
||||
( display Capacitor stipple7 lineStyle0 tan tan outlineStipple)
|
||||
( display markerErr x solid white white outlineStipple)
|
||||
( display unknown stipple0 solid yellow yellow solid )
|
||||
( display annotate stipple0 solid orange orange solid )
|
||||
( display P1ConNet x solid red red outlineStipple)
|
||||
( display hilite3 stipple0 solid cyan cyan solid )
|
||||
( display winActiveBanner solid solid winColor3 winColor3 solid )
|
||||
( display pinLbl stipple0 solid red red solid )
|
||||
( display device2 stipple0 lineStyle1 green green solid )
|
||||
( display grid stipple0 solid slate slate solid )
|
||||
( display winBackground solid solid winBack winBack solid )
|
||||
( display Metal1Net dots4 lineStyle0 blue blue outlineStipple)
|
||||
( display hilite2 stipple0 solid tan tan solid )
|
||||
( display annotate8 stipple0 solid tan tan solid )
|
||||
( display hilite5 stipple0 solid lime lime solid )
|
||||
( display annotate9 stipple0 solid green green solid )
|
||||
( display Metal2Net dots4 lineStyle0 magenta magenta outlineStipple)
|
||||
( display Metal3Pin stipple0 solid navy navy solid )
|
||||
( display hilite4 stipple0 solid gray gray solid )
|
||||
( display y0 stipple0 solid gray gray solid )
|
||||
( display supply stipple0 solid lime lime solid )
|
||||
( display ActiveNet dots4 lineStyle0 yellow yellow outlineStipple)
|
||||
( display hilite7 stipple0 solid cream cream solid )
|
||||
( display y1 stipple0 solid brown brown solid )
|
||||
( display defaultPacket x solid chocolate winColor2 outlineStipple)
|
||||
( display Via2Net cross solid navy navy outlineStipple)
|
||||
( display NselectNet dots4 solid green green outlineStipple)
|
||||
( display Unrouted8 stipple0 lineStyle1 gold gold solid )
|
||||
( display hilite6 stipple0 solid orange orange solid )
|
||||
( display y2 stipple0 solid red red solid )
|
||||
( display winBorder solid solid winColor2 winColor2 solid )
|
||||
( display Nwell dats5 thickLine slate slate outlineStipple)
|
||||
( display Unrouted9 stipple0 lineStyle1 silver silver solid )
|
||||
( display hilite9 stipple0 solid pink pink solid )
|
||||
( display SiBlock blank dashed tan tan outline )
|
||||
( display y3 stipple0 solid orange orange solid )
|
||||
( display prBoundaryBnd stipple0 solid cyan cyan solid )
|
||||
( display winForeground solid solid winFore winFore solid )
|
||||
( display hilite8 stipple0 solid magenta magenta solid )
|
||||
( display y4 stipple0 solid yellow yellow solid )
|
||||
( display Pselect dots1 solid brown brown outlineStipple)
|
||||
( display winInactiveBanner solid solid winColor4 winColor4 solid )
|
||||
( display designFlow9 stipple1 lineStyle0 orange orange outlineStipple)
|
||||
( display winButton solid solid winFore winFore solid )
|
||||
( display y5 stipple0 solid green green solid )
|
||||
( display hiz stipple0 solid orange orange solid )
|
||||
( display drive stipple0 solid blue blue solid )
|
||||
( display wireFlt stipple0 dashed red red solid )
|
||||
( display instanceLbl stipple0 solid gold gold solid )
|
||||
( display P2ConNet x lineStyle0 orange orange outlineStipple)
|
||||
( display designFlow8 stipple1 lineStyle0 navy navy outlineStipple)
|
||||
( display y6 stipple0 solid blue blue solid )
|
||||
( display PwellNet dots4 lineStyle0 slate slate outlineStipple)
|
||||
( display P1Con solid solid red red solid )
|
||||
( display CapWell dagger solid slate slate outlineStipple)
|
||||
( display y7 stipple0 solid purple purple solid )
|
||||
( display ViaX solid solid magenta magenta solid )
|
||||
( display HR x solid chocolate winColor2 outlineStipple)
|
||||
( display HRnet x solid chocolate winColor2 outlineStipple)
|
||||
)
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
import os
|
||||
CWD = os.environ.get("OPENRAM_TECH") + "/scn3me_subm/tf"
|
||||
ui().importCds("default", CWD+"/display.drf", CWD+"/mosis.tf", 1000, 1, CWD+"/layers.map")
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
Pwell drawing 41 0
|
||||
Nwell drawing 42 0
|
||||
Active drawing 43 0
|
||||
Poly1 drawing 46 0
|
||||
Pselect drawing 45 0
|
||||
Nselect drawing 44 0
|
||||
contact drawing 25 0
|
||||
P1Con drawing 47 0
|
||||
ActX drawing 48 0
|
||||
Metal1 drawing 49 0
|
||||
Via drawing 50 0
|
||||
Metal2 drawing 51 0
|
||||
Via2 drawing 61 0
|
||||
Metal3 drawing 62 0
|
||||
Glass drawing 52 0
|
||||
text drawing 83 0
|
||||
|
|
@ -0,0 +1,848 @@
|
|||
; Generated on Sep 28 16:05:23 1998
|
||||
; with @(#)$CDS: icfb.exe version 4.4.1 06/17/98 23:40 (cds10067) $
|
||||
;
|
||||
; Matt Clapp fixed: October 10, 2002
|
||||
; added via devices, deleted useless app-specific crap,
|
||||
; added lxExtractRules so undo in layout editor doesn't
|
||||
; complain.
|
||||
|
||||
|
||||
;********************************
|
||||
; LAYER DEFINITION
|
||||
;********************************
|
||||
|
||||
layerDefinitions(
|
||||
techLayers(
|
||||
;( LayerName Layer# Abbreviation )
|
||||
;( --------- ------ ------------ )
|
||||
;User-Defined Layers:
|
||||
( P2Con 3 P2Con )
|
||||
( Poly2 7 Poly2 )
|
||||
( Pbase 10 Pbase )
|
||||
( Resistor 16 Resisto )
|
||||
( Capacitor 17 Capacit )
|
||||
( Diode 18 Diode )
|
||||
( SiBlock 29 SiBlock )
|
||||
( HR 34 HR )
|
||||
( Pwell 41 Pwell )
|
||||
( Nwell 42 Nwell )
|
||||
( Active 43 Active )
|
||||
( Pselect 44 Pselect )
|
||||
( Nselect 45 Nselect )
|
||||
( Poly1 46 Poly1 )
|
||||
( P1Con 47 P1Con )
|
||||
( ActX 48 ActX )
|
||||
( Metal1 49 Metal1 )
|
||||
( Via 50 Via )
|
||||
( Metal2 51 Metal2 )
|
||||
( Glass 52 Glass )
|
||||
( CapWell 59 CapWell )
|
||||
( XP 60 XP )
|
||||
( Via2 61 Via2 )
|
||||
( Metal3 62 Metal3 )
|
||||
( A1 80 A1 )
|
||||
( A2 81 A2 )
|
||||
( comment 117 comment )
|
||||
;System-Reserved Layers:
|
||||
( Unrouted 200 Unroute )
|
||||
( Row 201 Row )
|
||||
( Group 202 Group )
|
||||
( Cannotoccupy 203 Cannoto )
|
||||
( Canplace 204 Canplac )
|
||||
( hardFence 205 hardFen )
|
||||
( softFence 206 softFen )
|
||||
( y0 207 y0 )
|
||||
( y1 208 y1 )
|
||||
( y2 209 y2 )
|
||||
( y3 210 y3 )
|
||||
( y4 211 y4 )
|
||||
( y5 212 y5 )
|
||||
( y6 213 y6 )
|
||||
( y7 214 y7 )
|
||||
( y8 215 y8 )
|
||||
( y9 216 y9 )
|
||||
( designFlow 217 designF )
|
||||
( stretch 218 stretch )
|
||||
( edgeLayer 219 edgeLay )
|
||||
( changedLayer 220 changed )
|
||||
( unset 221 unset )
|
||||
( unknown 222 unknown )
|
||||
( spike 223 spike )
|
||||
( hiz 224 hiz )
|
||||
( resist 225 resist )
|
||||
( drive 226 drive )
|
||||
( supply 227 supply )
|
||||
( wire 228 wire )
|
||||
( pin 229 pin )
|
||||
( text 230 text )
|
||||
( device 231 device )
|
||||
( border 232 border )
|
||||
( snap 233 snap )
|
||||
( align 234 align )
|
||||
( prBoundary 235 prBound )
|
||||
( instance 236 instanc )
|
||||
( annotate 237 annotat )
|
||||
( marker 238 marker )
|
||||
( select 239 select )
|
||||
( grid 251 grid )
|
||||
( axis 252 axis )
|
||||
( hilite 253 hilite )
|
||||
( background 254 backgro )
|
||||
) ;techLayers
|
||||
|
||||
techPurposes(
|
||||
;( PurposeName Purpose# Abbreviation )
|
||||
;( ----------- -------- ------------ )
|
||||
;User-Defined Purposes:
|
||||
;System-Reserved Purposes:
|
||||
( warning 234 wng )
|
||||
( tool1 235 tl1 )
|
||||
( tool0 236 tl0 )
|
||||
( label 237 lbl )
|
||||
( flight 238 flt )
|
||||
( error 239 err )
|
||||
( annotate 240 ant )
|
||||
( drawing1 241 dr1 )
|
||||
( drawing2 242 dr2 )
|
||||
( drawing3 243 dr3 )
|
||||
( drawing4 244 dr4 )
|
||||
( drawing5 245 dr5 )
|
||||
( drawing6 246 dr6 )
|
||||
( drawing7 247 dr7 )
|
||||
( drawing8 248 dr8 )
|
||||
( drawing9 249 dr9 )
|
||||
( boundary 250 bnd )
|
||||
( pin 251 pin )
|
||||
( drawing 252 drw )
|
||||
( net 253 net )
|
||||
( cell 254 cel )
|
||||
( all 255 all )
|
||||
) ;techPurposes
|
||||
|
||||
techLayerPurposePriorities(
|
||||
;layers are ordered from lowest to highest priority
|
||||
; (higher priority is drawn on top of lower priority)
|
||||
;( LayerName Purpose )
|
||||
;( --------- ------- )
|
||||
( background drawing )
|
||||
( grid drawing )
|
||||
( grid drawing1 )
|
||||
( Nwell drawing )
|
||||
( Pwell drawing )
|
||||
( CapWell drawing )
|
||||
( Pselect drawing )
|
||||
( Nselect drawing )
|
||||
( Active drawing )
|
||||
( ActX drawing )
|
||||
( SiBlock drawing )
|
||||
( HR drawing )
|
||||
( Poly1 drawing )
|
||||
( P1Con drawing )
|
||||
( Poly2 drawing )
|
||||
( P2Con drawing )
|
||||
( Metal1 drawing )
|
||||
( Via drawing )
|
||||
( Metal2 drawing )
|
||||
( Via2 drawing )
|
||||
( Metal3 drawing )
|
||||
( annotate drawing )
|
||||
( annotate drawing1 )
|
||||
( annotate drawing2 )
|
||||
( annotate drawing3 )
|
||||
( annotate drawing4 )
|
||||
( annotate drawing5 )
|
||||
( annotate drawing6 )
|
||||
( annotate drawing7 )
|
||||
( annotate drawing8 )
|
||||
( annotate drawing9 )
|
||||
( Poly1 pin )
|
||||
( Metal1 pin )
|
||||
( Metal2 pin )
|
||||
( Metal3 pin )
|
||||
( Glass drawing )
|
||||
( XP drawing )
|
||||
( prBoundary drawing )
|
||||
( prBoundary boundary )
|
||||
( instance drawing )
|
||||
( prBoundary label )
|
||||
( instance label )
|
||||
( Row drawing )
|
||||
( Nwell net )
|
||||
( align drawing )
|
||||
( Pwell net )
|
||||
( CapWell net )
|
||||
( hardFence drawing )
|
||||
( Active net )
|
||||
( softFence drawing )
|
||||
( Row label )
|
||||
( Group drawing )
|
||||
( Group label )
|
||||
( Cannotoccupy drawing )
|
||||
( Cannotoccupy boundary )
|
||||
( Canplace drawing )
|
||||
( ActX net )
|
||||
( A2 drawing )
|
||||
( A1 drawing )
|
||||
( comment drawing )
|
||||
( border drawing )
|
||||
( Pselect net )
|
||||
( Nselect net )
|
||||
( SiBlock net )
|
||||
( HR net )
|
||||
( wire drawing )
|
||||
( Poly1 net )
|
||||
( wire label )
|
||||
( P1Con net )
|
||||
( wire flight )
|
||||
( Metal1 net )
|
||||
( device annotate )
|
||||
( Metal2 net )
|
||||
( device label )
|
||||
( Via net )
|
||||
( Metal3 net )
|
||||
( Via2 net )
|
||||
( pin label )
|
||||
( text drawing )
|
||||
( pin drawing )
|
||||
( text drawing1 )
|
||||
( pin annotate )
|
||||
( device drawing )
|
||||
( axis drawing )
|
||||
( edgeLayer drawing )
|
||||
( edgeLayer pin )
|
||||
( snap drawing )
|
||||
( stretch drawing )
|
||||
( y0 drawing )
|
||||
( y1 drawing )
|
||||
( y2 drawing )
|
||||
( y3 drawing )
|
||||
( y4 drawing )
|
||||
( y5 drawing )
|
||||
( y6 drawing )
|
||||
( y7 drawing )
|
||||
( y8 drawing )
|
||||
( y9 drawing )
|
||||
( hilite drawing )
|
||||
( hilite drawing1 )
|
||||
( hilite drawing2 )
|
||||
( hilite drawing3 )
|
||||
( hilite drawing4 )
|
||||
( hilite drawing5 )
|
||||
( hilite drawing6 )
|
||||
( hilite drawing7 )
|
||||
( hilite drawing8 )
|
||||
( hilite drawing9 )
|
||||
( select drawing )
|
||||
( drive drawing )
|
||||
( hiz drawing )
|
||||
( resist drawing )
|
||||
( spike drawing )
|
||||
( supply drawing )
|
||||
( unknown drawing )
|
||||
( unset drawing )
|
||||
( designFlow drawing )
|
||||
( designFlow drawing1 )
|
||||
( designFlow drawing2 )
|
||||
( designFlow drawing3 )
|
||||
( designFlow drawing4 )
|
||||
( designFlow drawing5 )
|
||||
( designFlow drawing6 )
|
||||
( designFlow drawing7 )
|
||||
( designFlow drawing8 )
|
||||
( designFlow drawing9 )
|
||||
( changedLayer tool0 )
|
||||
( changedLayer tool1 )
|
||||
( marker warning )
|
||||
( marker error )
|
||||
( device drawing1 )
|
||||
( Pbase drawing )
|
||||
( Pbase net )
|
||||
( Resistor net )
|
||||
( Resistor drawing )
|
||||
( Capacitor net )
|
||||
( Capacitor drawing )
|
||||
( Diode net )
|
||||
( Diode drawing )
|
||||
( Poly2 net )
|
||||
( P2Con net )
|
||||
( device drawing2 )
|
||||
( Unrouted drawing )
|
||||
( text drawing2 )
|
||||
( Unrouted drawing1 )
|
||||
( Unrouted drawing2 )
|
||||
( Unrouted drawing3 )
|
||||
( Unrouted drawing4 )
|
||||
( Unrouted drawing5 )
|
||||
( Unrouted drawing6 )
|
||||
( Unrouted drawing7 )
|
||||
( Unrouted drawing8 )
|
||||
( Unrouted drawing9 )
|
||||
) ;techLayerPurposePriorities
|
||||
|
||||
techDisplays(
|
||||
;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid )
|
||||
;( --------- ------- ------ --- --- --------- ------- ----- )
|
||||
( background drawing background t nil nil nil nil )
|
||||
( grid drawing grid t nil nil nil nil )
|
||||
( grid drawing1 grid1 t nil nil nil nil )
|
||||
( Nwell drawing Nwell t t t t t )
|
||||
( Pwell drawing Pwell t t t t nil )
|
||||
( Active drawing Active t t t t t )
|
||||
( ActX drawing ActX t t t t t )
|
||||
( Pselect drawing Pselect t t t t t )
|
||||
( Nselect drawing Nselect t t t t t )
|
||||
( SiBlock drawing SiBlock t t t t t )
|
||||
( HR drawing HR t t t t t )
|
||||
( CapWell drawing CapWell t t t t t )
|
||||
( Poly1 drawing Poly1 t t t t t )
|
||||
( P1Con drawing P1Con t t t t t )
|
||||
( Metal1 drawing Metal1 t t t t t )
|
||||
( Via drawing Via t t t t t )
|
||||
( Metal2 drawing Metal2 t t t t t )
|
||||
( annotate drawing annotate t t nil t nil )
|
||||
( annotate drawing1 annotate1 t t nil t nil )
|
||||
( annotate drawing2 annotate2 t t nil t nil )
|
||||
( annotate drawing3 annotate3 t t nil t nil )
|
||||
( annotate drawing4 annotate4 t t nil t nil )
|
||||
( annotate drawing5 annotate5 t t nil t nil )
|
||||
( annotate drawing6 annotate6 t t nil t nil )
|
||||
( annotate drawing7 annotate7 t t nil t nil )
|
||||
( annotate drawing8 annotate8 t t nil t nil )
|
||||
( annotate drawing9 annotate9 t t nil t nil )
|
||||
( Via2 drawing Via2 t t t t t )
|
||||
( Metal3 drawing Metal3 t t t t t )
|
||||
( Glass drawing Glass t t t nil t )
|
||||
( XP drawing XP t t t nil t )
|
||||
( Metal1 pin Metal1Pin t t t nil t )
|
||||
( Metal2 pin Metal2Pin t t t nil t )
|
||||
( Metal3 pin Metal3Pin t t t nil t )
|
||||
( Poly1 pin Poly1Pin t t t nil t )
|
||||
( prBoundary drawing prBoundary t t nil t nil )
|
||||
( prBoundary boundary prBoundaryBnd t t nil t nil )
|
||||
( instance drawing instance t t nil t t )
|
||||
( prBoundary label prBoundaryLbl t t t t nil )
|
||||
( instance label instanceLbl t t t t nil )
|
||||
( Row drawing Row t t t t nil )
|
||||
( Nwell net NwellNet t t t nil nil )
|
||||
( align drawing align t t nil t nil )
|
||||
( Pwell net PwellNet t t t nil nil )
|
||||
( CapWell net CapWellNet t t t nil nil )
|
||||
( SiBlock net SiBlockNet t t t nil nil )
|
||||
( HR net HRnet t t t nil nil )
|
||||
( hardFence drawing hardFence t t t t nil )
|
||||
( Active net ActiveNet t t t nil nil )
|
||||
( softFence drawing softFence t t t t nil )
|
||||
( Row label RowLbl t t t t nil )
|
||||
( Group drawing Group t t t t nil )
|
||||
( Group label GroupLbl t t t t nil )
|
||||
( Cannotoccupy drawing Cannotoccupy t t t t nil )
|
||||
( Cannotoccupy boundary CannotoccupyBnd t t t t nil )
|
||||
( Canplace drawing Canplace t t t t nil )
|
||||
( ActX net ActXNet t t t nil nil )
|
||||
( A2 drawing A2 t t t t nil )
|
||||
( A1 drawing A1 t t t t nil )
|
||||
( comment drawing comment t t t t nil )
|
||||
( border drawing border t t t t nil )
|
||||
( Pselect net PselectNet t t t nil nil )
|
||||
( Nselect net NselectNet t t t nil nil )
|
||||
( wire drawing wire t t t t nil )
|
||||
( Poly1 net Poly1Net t t t nil nil )
|
||||
( wire label wireLbl t t t t nil )
|
||||
( P1Con net P1ConNet t t t nil nil )
|
||||
( wire flight wireFlt t t t t nil )
|
||||
( Metal1 net Metal1Net t t t nil nil )
|
||||
( device annotate deviceAnt t t t t nil )
|
||||
( Metal2 net Metal2Net t t t nil nil )
|
||||
( Metal3 net Metal3Net t t t nil nil )
|
||||
( device label deviceLbl t t t t nil )
|
||||
( Via net ViaNet t t t nil nil )
|
||||
( Via2 net Via2Net t t t nil nil )
|
||||
( pin label pinLbl t t t t nil )
|
||||
( text drawing text t t t t t )
|
||||
( pin drawing pin t t t t nil )
|
||||
( text drawing1 text1 t t t t nil )
|
||||
( pin annotate pinAnt t t t t nil )
|
||||
( device drawing device t t t t nil )
|
||||
( axis drawing axis t t t t nil )
|
||||
( edgeLayer drawing edgeLayer t t nil t nil )
|
||||
( edgeLayer pin edgeLayerPin t t nil t nil )
|
||||
( snap drawing snap t t nil t nil )
|
||||
( stretch drawing stretch t t nil t nil )
|
||||
( y0 drawing y0 t t nil t nil )
|
||||
( y1 drawing y1 t t nil t nil )
|
||||
( y2 drawing y2 t t nil t nil )
|
||||
( y3 drawing y3 t t nil t nil )
|
||||
( y4 drawing y4 t t nil t nil )
|
||||
( y5 drawing y5 t t nil t nil )
|
||||
( y6 drawing y6 t t nil t nil )
|
||||
( y7 drawing y7 t t nil t nil )
|
||||
( y8 drawing y8 t t nil t nil )
|
||||
( y9 drawing y9 t t nil t nil )
|
||||
( hilite drawing hilite t t nil t nil )
|
||||
( hilite drawing1 hilite1 t t t t nil )
|
||||
( hilite drawing2 hilite2 t t nil t nil )
|
||||
( hilite drawing3 hilite3 t t t t nil )
|
||||
( hilite drawing4 hilite4 t t t t nil )
|
||||
( hilite drawing5 hilite5 t t t t nil )
|
||||
( hilite drawing6 hilite6 t t t t nil )
|
||||
( hilite drawing7 hilite7 t t t t nil )
|
||||
( hilite drawing8 hilite8 t t t t nil )
|
||||
( hilite drawing9 hilite9 t t t t nil )
|
||||
( select drawing select t t nil t nil )
|
||||
( drive drawing drive t t t t nil )
|
||||
( hiz drawing hiz t t t t nil )
|
||||
( resist drawing resist t t t t nil )
|
||||
( spike drawing spike t t t t nil )
|
||||
( supply drawing supply t t t t nil )
|
||||
( unknown drawing unknown t t t t nil )
|
||||
( unset drawing unset t t t t nil )
|
||||
( designFlow drawing designFlow t t t nil nil )
|
||||
( designFlow drawing1 designFlow1 t t t nil nil )
|
||||
( designFlow drawing2 designFlow2 t t t nil nil )
|
||||
( designFlow drawing3 designFlow3 t t t nil nil )
|
||||
( designFlow drawing4 designFlow4 t t t nil nil )
|
||||
( designFlow drawing5 designFlow5 t t t nil nil )
|
||||
( designFlow drawing6 designFlow6 t t t nil nil )
|
||||
( designFlow drawing7 designFlow7 t t t nil nil )
|
||||
( designFlow drawing8 designFlow8 t t t nil nil )
|
||||
( designFlow drawing9 designFlow9 t t t nil nil )
|
||||
( changedLayer tool0 changedLayerTl0 nil nil nil nil nil )
|
||||
( changedLayer tool1 changedLayerTl1 nil nil t nil nil )
|
||||
( marker warning markerWarn t t t t nil )
|
||||
( marker error markerErr t t t t nil )
|
||||
( device drawing1 device1 t t t t nil )
|
||||
( Poly2 net Poly2Net t t t nil nil )
|
||||
( Poly2 drawing Poly2 t t t t t )
|
||||
( P2Con net P2ConNet t t t nil nil )
|
||||
( P2Con drawing P2Con t t t t t )
|
||||
( Pbase net PbaseNet t t t nil nil )
|
||||
( Pbase drawing Pbase t t t t t )
|
||||
( Resistor net ResistorNet t t t nil nil )
|
||||
( Resistor drawing Resistor t t t t t )
|
||||
( Capacitor net CapacitorNet t t t nil nil )
|
||||
( Capacitor drawing Capacitor t t t t t )
|
||||
( Diode net DiodeNet t t t nil nil )
|
||||
( Diode drawing Diode t t t t t )
|
||||
( device drawing2 device2 t t t t nil )
|
||||
( Unrouted drawing Unrouted t t t t nil )
|
||||
( text drawing2 text2 t t t t nil )
|
||||
( Unrouted drawing1 Unrouted1 t t t t nil )
|
||||
( Unrouted drawing2 Unrouted2 t t t t nil )
|
||||
( Unrouted drawing3 Unrouted3 t t t t nil )
|
||||
( Unrouted drawing4 Unrouted4 t t t t nil )
|
||||
( Unrouted drawing5 Unrouted5 t t t t nil )
|
||||
( Unrouted drawing6 Unrouted6 t t t t nil )
|
||||
( Unrouted drawing7 Unrouted7 t t t t nil )
|
||||
( Unrouted drawing8 Unrouted8 t t t t nil )
|
||||
( Unrouted drawing9 Unrouted9 t t t t nil )
|
||||
) ;techDisplays
|
||||
|
||||
; I don't think the following is necessary (or used!)
|
||||
techLayerProperties(
|
||||
;( PropName Layer1 [ Layer2 ] PropValue )
|
||||
( contactLimit P2Con 10000 )
|
||||
( eqPinLimit P2Con 10000 )
|
||||
( horizontalJogLength P2Con 2147483648.000000 )
|
||||
( routingGrid P2Con 1.000000 )
|
||||
( verticalJogLength P2Con 2147483648.000000 )
|
||||
( routingGrid Poly2 1.000000 )
|
||||
( contactLimit Active 10000 )
|
||||
( eqPinLimit Active 10000 )
|
||||
( horizontalJogLength Active 2147483648.000000 )
|
||||
( routingGrid Active 1.000000 )
|
||||
( verticalJogLength Active 2147483648.000000 )
|
||||
( routingGrid Poly1 1.000000 )
|
||||
( contactLimit P1Con 10000 )
|
||||
( eqPinLimit P1Con 10000 )
|
||||
( horizontalJogLength P1Con 2147483648.000000 )
|
||||
( routingGrid P1Con 1.000000 )
|
||||
( verticalJogLength P1Con 2147483648.000000 )
|
||||
( contactLimit ActX 10000 )
|
||||
( eqPinLimit ActX 10000 )
|
||||
( horizontalJogLength ActX 2147483648.000000 )
|
||||
( routingGrid ActX 1.000000 )
|
||||
( verticalJogLength ActX 2147483648.000000 )
|
||||
( routingGrid Metal1 1.000000 )
|
||||
( contactLimit Via 10000 )
|
||||
( eqPinLimit Via 10000 )
|
||||
( horizontalJogLength Via 2147483648.000000 )
|
||||
( routingGrid Via 1.000000 )
|
||||
( verticalJogLength Via 2147483648.000000 )
|
||||
( routingGrid Metal2 1.000000 )
|
||||
)
|
||||
|
||||
) ;layerDefinitions
|
||||
|
||||
|
||||
;********************************
|
||||
; DEVICE RULES
|
||||
;********************************
|
||||
|
||||
devices(
|
||||
tcCreateCDSDeviceClass()
|
||||
|
||||
symContactDevice(
|
||||
;( deviceName viaLayer viaPurpose
|
||||
( VIA Via drawing
|
||||
|
||||
; layer1 purpose1 [implant1]
|
||||
Metal1 drawing
|
||||
|
||||
; layer2 purpose2 [implant2]
|
||||
Metal2 drawing
|
||||
|
||||
; width length [( row column xPitch yPitch xBias yBias )]
|
||||
; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ )
|
||||
2 2
|
||||
|
||||
; encLayer1 encLayer2 legalRegion )
|
||||
1 1 _NA_)
|
||||
) ;symContactDevice
|
||||
|
||||
symContactDevice(
|
||||
;( deviceName viaLayer viaPurpose
|
||||
( VIA2 Via2 drawing
|
||||
|
||||
; layer1 purpose1 [implant1]
|
||||
Metal2 drawing
|
||||
|
||||
; layer2 purpose2 [implant2]
|
||||
Metal3 drawing
|
||||
|
||||
; width length [( row column xPitch yPitch xBias yBias )]
|
||||
; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ )
|
||||
2 2
|
||||
|
||||
; encLayer1 encLayer2 legalRegion )
|
||||
1 2 _NA_)
|
||||
) ;symContactDevice
|
||||
|
||||
) ;devices
|
||||
|
||||
|
||||
;********************************
|
||||
; LAYER RULES
|
||||
;********************************
|
||||
|
||||
layerRules(
|
||||
streamLayers(
|
||||
;( layer streamNumber dataType translate )
|
||||
;( ----- ------------ -------- --------- )
|
||||
( ("background" "drawing") 0 0 nil )
|
||||
( ("grid" "drawing") 0 0 nil )
|
||||
( ("grid" "drawing1") 0 0 nil )
|
||||
( ("Nwell" "drawing") 42 0 t )
|
||||
( ("Pwell" "drawing") 41 0 t )
|
||||
( ("Active" "drawing") 43 0 t )
|
||||
( ("ActX" "drawing") 48 0 t )
|
||||
( ("Pselect" "drawing") 44 0 t )
|
||||
( ("Nselect" "drawing") 45 0 t )
|
||||
( ("Poly1" "drawing") 46 0 t )
|
||||
( ("P1Con" "drawing") 47 0 t )
|
||||
( ("Metal1" "drawing") 49 0 t )
|
||||
( ("Metal2" "drawing") 51 0 t )
|
||||
( ("annotate" "drawing") 0 0 nil )
|
||||
( ("annotate" "drawing1") 0 0 nil )
|
||||
( ("annotate" "drawing2") 0 0 nil )
|
||||
( ("annotate" "drawing3") 0 0 nil )
|
||||
( ("annotate" "drawing4") 0 0 nil )
|
||||
( ("annotate" "drawing5") 0 0 nil )
|
||||
( ("annotate" "drawing6") 0 0 nil )
|
||||
( ("annotate" "drawing7") 0 0 nil )
|
||||
( ("annotate" "drawing8") 0 0 nil )
|
||||
( ("annotate" "drawing9") 0 0 nil )
|
||||
( ("Via" "drawing") 50 0 t )
|
||||
( ("Glass" "drawing") 52 0 t )
|
||||
( ("XP" "drawing") 60 0 t )
|
||||
( ("Metal2" "pin") 0 0 nil )
|
||||
( ("Poly1" "pin") 0 0 nil )
|
||||
( ("prBoundary" "drawing") 0 0 nil )
|
||||
( ("Metal1" "pin") 0 0 nil )
|
||||
( ("prBoundary" "boundary") 0 0 nil )
|
||||
( ("instance" "drawing") 246 0 nil )
|
||||
( ("instance" "label") 0 0 nil )
|
||||
( ("Nwell" "net") 0 0 nil )
|
||||
( ("align" "drawing") 0 0 nil )
|
||||
( ("Pwell" "net") 0 0 nil )
|
||||
( ("hardFence" "drawing") 0 0 nil )
|
||||
( ("Active" "net") 0 0 nil )
|
||||
( ("softFence" "drawing") 0 0 nil )
|
||||
( ("ActX" "net") 0 0 nil )
|
||||
( ("A2" "drawing") 5 0 nil )
|
||||
( ("A1" "drawing") 2 0 nil )
|
||||
( ("comment" "drawing") 0 0 nil )
|
||||
( ("border" "drawing") 0 0 nil )
|
||||
( ("Pselect" "net") 0 0 nil )
|
||||
( ("Nselect" "net") 0 0 nil )
|
||||
( ("wire" "drawing") 0 0 nil )
|
||||
( ("Poly1" "net") 0 0 nil )
|
||||
( ("P1Con" "net") 0 0 nil )
|
||||
( ("Metal1" "net") 0 0 nil )
|
||||
( ("Metal2" "net") 0 0 nil )
|
||||
( ("device" "label") 0 0 nil )
|
||||
( ("Via" "net") 0 0 nil )
|
||||
( ("pin" "label") 0 0 nil )
|
||||
( ("text" "drawing") 63 0 t )
|
||||
( ("pin" "drawing") 0 0 nil )
|
||||
( ("device" "drawing") 0 0 nil )
|
||||
( ("axis" "drawing") 0 0 nil )
|
||||
( ("edgeLayer" "drawing") 0 0 nil )
|
||||
( ("edgeLayer" "pin") 0 0 nil )
|
||||
( ("snap" "drawing") 0 0 nil )
|
||||
( ("stretch" "drawing") 0 0 nil )
|
||||
( ("y0" "drawing") 0 0 nil )
|
||||
( ("y1" "drawing") 0 0 nil )
|
||||
( ("y2" "drawing") 0 0 nil )
|
||||
( ("y3" "drawing") 0 0 nil )
|
||||
( ("y4" "drawing") 0 0 nil )
|
||||
( ("y5" "drawing") 0 0 nil )
|
||||
( ("y6" "drawing") 0 0 nil )
|
||||
( ("y7" "drawing") 0 0 nil )
|
||||
( ("y8" "drawing") 0 0 nil )
|
||||
( ("y9" "drawing") 0 0 nil )
|
||||
( ("hilite" "drawing") 0 0 nil )
|
||||
( ("hilite" "drawing2") 0 0 nil )
|
||||
( ("select" "drawing") 0 0 nil )
|
||||
( ("drive" "drawing") 0 0 nil )
|
||||
( ("hiz" "drawing") 0 0 nil )
|
||||
( ("resist" "drawing") 0 0 nil )
|
||||
( ("spike" "drawing") 0 0 nil )
|
||||
( ("supply" "drawing") 0 0 nil )
|
||||
( ("unknown" "drawing") 0 0 nil )
|
||||
( ("unset" "drawing") 0 0 nil )
|
||||
( ("changedLayer" "tool0") 0 0 nil )
|
||||
( ("Resistor" "net") 0 0 nil )
|
||||
( ("Resistor" "drawing") 0 0 nil )
|
||||
( ("Capacitor" "net") 0 0 nil )
|
||||
( ("Capacitor" "drawing") 0 0 nil )
|
||||
( ("Diode" "net") 0 0 nil )
|
||||
( ("Diode" "drawing") 0 0 nil )
|
||||
( ("Poly2" "net") 0 0 nil )
|
||||
( ("Poly2" "drawing") 0 0 nil )
|
||||
( ("P2Con" "net") 0 0 nil )
|
||||
( ("P2Con" "drawing") 0 0 nil )
|
||||
( ("Pbase" "drawing") 0 0 nil )
|
||||
( ("Pbase" "net") 0 0 nil )
|
||||
( P2Con 0 0 nil )
|
||||
( Poly2 0 0 nil )
|
||||
( Pwell 0 0 nil )
|
||||
( Nwell 0 0 nil )
|
||||
( Active 0 0 nil )
|
||||
( Pselect 0 0 nil )
|
||||
( Nselect 0 0 nil )
|
||||
( Poly1 0 0 nil )
|
||||
( P1Con 0 0 nil )
|
||||
( ActX 0 0 nil )
|
||||
( Metal1 0 0 nil )
|
||||
( Via 0 0 nil )
|
||||
( Metal2 0 0 nil )
|
||||
( Glass 0 0 nil )
|
||||
( XP 0 0 nil )
|
||||
( ("Via2" "drawing") 50 0 t )
|
||||
( ("Via2" "net") 0 0 nil )
|
||||
( ("Metal3" "drawing") 50 0 t )
|
||||
( ("Metal3" "net") 0 0 nil )
|
||||
( ("Metal3" "pin") 0 0 nil )
|
||||
( ("CapWell" "drawing") 0 0 nil )
|
||||
( ("CapWell" "net") 0 0 nil )
|
||||
( ("SiBlock" "drawing") 0 0 nil )
|
||||
( ("SiBlock" "net") 0 0 nil )
|
||||
( ("HR" "drawing") 0 0 nil )
|
||||
( ("HR" "net") 0 0 nil )
|
||||
) ;streamLayers
|
||||
|
||||
viaLayers(
|
||||
;( layer1 viaLayer layer2 )
|
||||
;( ------ -------- ------ )
|
||||
( Metal2 Via2 Metal3 )
|
||||
( Metal1 Via Metal2 )
|
||||
( Active ActX Poly1 )
|
||||
( Poly1 P1Con Metal1 )
|
||||
( Poly2 P2Con Metal1 )
|
||||
) ;viaLayers
|
||||
|
||||
) ;layerRules
|
||||
|
||||
|
||||
;********************************
|
||||
; PHYSICAL RULES
|
||||
;********************************
|
||||
|
||||
physicalRules(
|
||||
orderedSpacingRules(
|
||||
;( rule layer1 layer2 value )
|
||||
;( ---- ------ ------ ----- )
|
||||
( minEnclosure "prBoundary" "Metal1" 0.0 )
|
||||
( minEnclosure "Metal2" "Via" 1.0 )
|
||||
( minEnclosure "Metal1" "Via" 1.0 )
|
||||
( minEnclosure "Metal1" "P1Con" 1.0 )
|
||||
( minEnclosure "Metal1" "ActX" 1.0 )
|
||||
( minEnclosure "Nselect" "Active" 2.0 )
|
||||
( minEnclosure "Pselect" "Active" 2.0 )
|
||||
( minEnclosure "Active" "ActX" 1.0 )
|
||||
( minEnclosure "Pwell" "Active" 5.0 )
|
||||
( minEnclosure "Nwell" "Active" 5.0 )
|
||||
) ;orderedSpacingRules
|
||||
|
||||
spacingRules(
|
||||
;( rule layer1 layer2 value )
|
||||
;( ---- ------ ------ ----- )
|
||||
( minSpacing "P2Con" 2.0 )
|
||||
( minSpacing "Poly2" 3.0 )
|
||||
( minSpacing "Pwell" 9.0 )
|
||||
( minSpacing "Nwell" 9.0 )
|
||||
( minSpacing "Active" 3.0 )
|
||||
( minSpacing "Pselect" 2.0 )
|
||||
( minSpacing "Nselect" 2.0 )
|
||||
( minSpacing "Poly1" 2.0 )
|
||||
( minSpacing "P1Con" 2.0 )
|
||||
( minSpacing "ActX" 2.0 )
|
||||
( minSpacing "Metal1" 3.0 )
|
||||
( minSpacing "Via" 3.0 )
|
||||
( minSpacing "Via2" 3.0 )
|
||||
( minSpacing "Metal2" 3.0 )
|
||||
( minSpacing "Metal3" 4.0 )
|
||||
( minSpacing "Glass" 75.0 )
|
||||
( minSpacing "XP" 100.0 )
|
||||
( minSpacing "Metal2" 4.0 )
|
||||
( minSpacing "P1Con" "Via" 2.0 )
|
||||
( minSpacing "ActX" "Via" 2.0 )
|
||||
( minSpacing "ActX" "P2Con" 2.0 )
|
||||
( minSpacing "Poly2" "P2Con" 4.0 )
|
||||
( minSpacing "Poly1" "P1Con" 4.0 )
|
||||
( minSpacing "ActX" "P1Con" 2.0 )
|
||||
( minSpacing "Active" "P1Con" 2.0 )
|
||||
( minSpacing "Active" "Poly2" 2.0 )
|
||||
( minSpacing "Poly1" "Poly2" 2.0 )
|
||||
( minSpacing "Active" "Poly1" 2.0 )
|
||||
( minSpacing "ActX" "Poly1" 2.0 )
|
||||
( minSpacing "Pselect" "Nselect" 0.0 )
|
||||
( minSpacing "Nwell" "Pwell" 9.0 )
|
||||
( minWidth "P2Con" 2.0 )
|
||||
( minWidth "Poly2" 3.0 )
|
||||
( minWidth "Pwell" 10.0 )
|
||||
( minWidth "Nwell" 10.0 )
|
||||
( minWidth "Active" 3.0 )
|
||||
( minWidth "Pselect" 2.0 )
|
||||
( minWidth "Nselect" 2.0 )
|
||||
( minWidth "Poly1" 2.0 )
|
||||
( minWidth "P1Con" 2.0 )
|
||||
( minWidth "ActX" 2.0 )
|
||||
( minWidth "Metal1" 4.0 )
|
||||
( minWidth "Via" 2.0 )
|
||||
( minWidth "Metal2" 4.0 )
|
||||
( minWidth "Glass" 75.0 )
|
||||
( minWidth "XP" 100.0 )
|
||||
( minWidth "Metal3" 6.0 )
|
||||
) ;spacingRules
|
||||
|
||||
mfgGridResolution(
|
||||
( 1.000000 )
|
||||
) ;mfgGridResolution
|
||||
|
||||
) ;physicalRules
|
||||
|
||||
|
||||
;********************************
|
||||
; ELECTRICAL RULES
|
||||
;********************************
|
||||
|
||||
electricalRules(
|
||||
characterizationRules(
|
||||
;( rule layer1 layer2 value )
|
||||
;( ---- ------ ------ ----- )
|
||||
( areaCap "P2Con" 0.0 )
|
||||
( areaCap "Poly2" 0.0 )
|
||||
( areaCap "Active" 0.0 )
|
||||
( areaCap "Poly1" 6e-05 )
|
||||
( areaCap "P1Con" 0.0 )
|
||||
( areaCap "ActX" 0.0 )
|
||||
( areaCap "Metal1" 2.6e-05 )
|
||||
( areaCap "Via" 0.0 )
|
||||
( areaCap "Metal2" 1.6e-05 )
|
||||
( edgeCapacitance "P2Con" 0.0 )
|
||||
( edgeCapacitance "Poly2" 0.0 )
|
||||
( edgeCapacitance "Active" 0.0 )
|
||||
( edgeCapacitance "Poly1" 0.0 )
|
||||
( edgeCapacitance "P1Con" 0.0 )
|
||||
( edgeCapacitance "ActX" 0.0 )
|
||||
( edgeCapacitance "Metal1" 0.0 )
|
||||
( edgeCapacitance "Via" 0.0 )
|
||||
( edgeCapacitance "Metal2" 0.0 )
|
||||
( sheetRes "P2Con" 0.0 )
|
||||
( sheetRes "Poly2" 0.0 )
|
||||
( sheetRes "Active" 0.0 )
|
||||
( sheetRes "Poly1" 23.0 )
|
||||
( sheetRes "P1Con" 0.0 )
|
||||
( sheetRes "ActX" 0.0 )
|
||||
( sheetRes "Metal1" 0.04 )
|
||||
( sheetRes "Via" 0.0 )
|
||||
( sheetRes "Metal2" 0.07 )
|
||||
( currentDensity "P2Con" 1.0 )
|
||||
( currentDensity "Poly2" 1.0 )
|
||||
( currentDensity "Active" 1.0 )
|
||||
( currentDensity "Poly1" 1.0 )
|
||||
( currentDensity "P1Con" 1.0 )
|
||||
( currentDensity "ActX" 1.0 )
|
||||
( currentDensity "Metal1" 1.0 )
|
||||
( currentDensity "Via" 1.0 )
|
||||
( currentDensity "Metal2" 1.0 )
|
||||
) ;characterizationRules
|
||||
|
||||
) ;electricalRules
|
||||
|
||||
|
||||
;********************************
|
||||
; LAYOUT EDITOR RULES
|
||||
;********************************
|
||||
; specifies the ordering of the layers in the LSW
|
||||
|
||||
leRules(
|
||||
leLswLayers(
|
||||
;( layer purpose )
|
||||
; ----- ------- )
|
||||
( Nwell drawing )
|
||||
( Pselect drawing )
|
||||
( Nselect drawing )
|
||||
( Active drawing )
|
||||
( ActX drawing )
|
||||
( Poly1 drawing )
|
||||
( P1Con drawing )
|
||||
( Metal1 drawing )
|
||||
( Via drawing )
|
||||
( Metal2 drawing )
|
||||
( Via2 drawing )
|
||||
( Metal3 drawing )
|
||||
( Poly1 pin )
|
||||
( Metal1 pin )
|
||||
( Metal2 pin )
|
||||
( Metal3 pin )
|
||||
( Poly2 drawing )
|
||||
( P2Con drawing )
|
||||
( instance drawing )
|
||||
( text drawing )
|
||||
( CapWell drawing )
|
||||
( SiBlock drawing )
|
||||
( HR drawing )
|
||||
( Pbase drawing )
|
||||
( Resistor drawing )
|
||||
( Capacitor drawing )
|
||||
( Diode drawing )
|
||||
( Glass drawing )
|
||||
( XP drawing )
|
||||
|
||||
) ;leLswLayers
|
||||
) ;leRules
|
||||
|
||||
|
||||
;********************************
|
||||
; VIRTUOSO XL RULES
|
||||
;********************************
|
||||
; specifies the ordering of the layers in the LSW
|
||||
|
||||
lxRules(
|
||||
lxExtractLayers(
|
||||
(Metal1 Metal2 Metal3)
|
||||
) ;lxExtractLayers
|
||||
) ;lxRules
|
||||
|
||||
Loading…
Reference in New Issue