diff --git a/compiler/base/design.py b/compiler/base/design.py index 39ad1792..1d38f5a9 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -120,3 +120,10 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout): for i in self.insts: text+=str(i)+",\n" return text + + def analytical_power(self, proc, vdd, temp, load): + """ Get total power of a module """ + total_module_power = self.return_power() + for inst in self.insts: + total_module_power += inst.mod.analytical_power(proc, vdd, temp, load) + return total_module_power diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 81ca717d..7b73a684 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -121,7 +121,8 @@ class layout(lef.lef): def add_inst(self, name, mod, offset=[0,0], mirror="R0",rotate=0): """Adds an instance of a mod to this module""" self.insts.append(geometry.instance(name, mod, offset, mirror, rotate)) - debug.info(4, "adding instance" + ",".join(x.name for x in self.insts)) + debug.info(3, "adding instance {}".format(self.insts[-1])) + debug.info(4, "instance list: " + ",".join(x.name for x in self.insts)) return self.insts[-1] def get_inst(self, name): @@ -453,6 +454,7 @@ class layout(lef.lef): def gds_write_file(self, newLayout): """Recursive GDS write function""" + # Visited means that we already prepared self.gds for this subtree if self.visited: return for i in self.insts: @@ -468,10 +470,11 @@ class layout(lef.lef): """Write the entire gds of the object to the file.""" debug.info(3, "Writing to {0}".format(gds_name)) - #self.gds = gdsMill.VlsiLayout(name=self.name,units=GDS["unit"]) writer = gdsMill.Gds2writer(self.gds) - # clear the visited flag for the traversal - self.clear_visited() + # MRG: 3/2/18 We don't want to clear the visited flag since + # this would result in duplicates of all instances being placed in self.gds + # which may have been previously processed! + #self.clear_visited() # recursively create all the remaining objects self.gds_write_file(self.gds) # populates the xyTree data structure for gds diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index d218227e..71921412 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -97,8 +97,8 @@ class spice(verilog.verilog): for i in range(len(self.spice)): self.spice[i] = self.spice[i].rstrip(" \n") - # find first subckt line in the file - subckt = re.compile("^.subckt", re.IGNORECASE) + # find the correct subckt line in the file + subckt = re.compile("^.subckt {}".format(self.name), re.IGNORECASE) subckt_line = filter(subckt.search, self.spice)[0] # parses line into ports and remove subckt self.pins = subckt_line.split(" ")[2:] @@ -214,6 +214,9 @@ class spice(verilog.verilog): def generate_rc_net(self,lump_num, wire_length, wire_width): return wire_spice_model(lump_num, wire_length, wire_width) + + def return_power(self, dynamic=0.0, leakage=0.0): + return power_data(dynamic, leakage) class delay_data: """ @@ -246,6 +249,37 @@ class delay_data: assert isinstance(other,delay_data) return delay_data(other.delay + self.delay, self.slew) + +class power_data: + """ + This is the power class to represent the power information + Dynamic and leakage power are stored as a single object with this class. + """ + def __init__(self, dynamic=0.0, leakage=0.0): + """ init function support two init method""" + # will take single input as a coordinate + self.dynamic = dynamic + self.leakage = leakage + + def __str__(self): + """ override print function output """ + return "Power Data: Dynamic "+str(self.dynamic)+", Leakage "+str(self.leakage)+" in nW" + + def __add__(self, other): + """ + Override - function (left), for power_data: a+b != b+a + """ + assert isinstance(other,power_data) + return power_data(other.dynamic + self.dynamic, + other.leakage + self.leakage) + + def __radd__(self, other): + """ + Override - function (left), for power_data: a+b != b+a + """ + assert isinstance(other,power_data) + return power_data(other.dynamic + self.dynamic, + other.leakage + self.leakage) class wire_spice_model: diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index c4efa25c..ca51f358 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -721,17 +721,24 @@ class delay(): delay_hl.append(bank_delay.delay/1e3) slew_lh.append(bank_delay.slew/1e3) slew_hl.append(bank_delay.slew/1e3) - + + power = sram.analytical_power(self.process, self.vdd_voltage, self.temperature, load) + #convert from nW to mW + power.dynamic /= 1e6 + power.leakage /= 1e6 + debug.info(1,"Dynamic Power: {0} mW".format(power.dynamic)) + debug.info(1,"Leakage Power: {0} mW".format(power.leakage)) + data = {"min_period": 0, "delay_lh": delay_lh, "delay_hl": delay_hl, "slew_lh": slew_lh, "slew_hl": slew_hl, - "read0_power": 0, - "read1_power": 0, - "write0_power": 0, - "write1_power": 0, - "leakage_power": 0 + "read0_power": power.dynamic, + "read1_power": power.dynamic, + "write0_power": power.dynamic, + "write1_power": power.dynamic, + "leakage_power": power.leakage } return data diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 142d2678..25b8199c 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -1228,3 +1228,4 @@ class bank(design.design): result = msf_addr_delay + decoder_delay + word_driver_delay \ + bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay return result + diff --git a/compiler/modules/bitcell.py b/compiler/modules/bitcell.py index 9f110a41..2f8a843c 100644 --- a/compiler/modules/bitcell.py +++ b/compiler/modules/bitcell.py @@ -34,7 +34,8 @@ class bitcell(design.design): c_para = spice["min_tx_drain_c"] result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew, swing = swing) return result - + + def list_bitcell_pins(self, col, row): # Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array bitcell_pins = ["bl[{0}]".format(col), @@ -56,4 +57,12 @@ class bitcell(design.design): column_pins = ["BL", "BR"] return column_pins - \ No newline at end of file + + def analytical_power(self, proc, vdd, temp, load): + """Bitcell power in nW. Only characterizes leakage.""" + from tech import spice + leakage = spice["bitcell_leakage"] + dynamic = 0 #temporary + total_power = self.return_power(dynamic, leakage) + return total_power + diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 83a0e236..7a0fbb56 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -179,6 +179,25 @@ class bitcell_array(design.design): #we do not consider the delay over the wire for now return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay, wl_to_cell_delay.slew) + + def analytical_power(self, proc, vdd, temp, load): + """Power of Bitcell array and bitline in nW.""" + from tech import drc + + # Dynamic Power from Bitline + bl_wire = self.gen_bl_wire() + cell_load = 2 * bl_wire.return_input_cap() + bl_swing = 0.1 #This should probably be defined in the tech file or input + freq = spice["default_event_rate"] + bitline_dynamic = bl_swing*cell_load*vdd*vdd*freq #not sure if calculation is correct + + #Calculate the bitcell power which currently only includes leakage + cell_power = self.cell.analytical_power(proc, vdd, temp, load) + + #Leakage power grows with entire array and bitlines. + total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size, + cell_power.leakage * self.column_size * self.row_size) + return total_power def gen_wl_wire(self): wl_wire = self.generate_rc_net(int(self.column_size), self.width, drc["minwidth_metal1"]) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index a006068c..c9dbd436 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -98,7 +98,7 @@ class control_logic(design.design): # GAP between main control and replica bitline self.replica_bitline_gap = 2*self.m2_pitch - + def add_modules(self): @@ -688,4 +688,4 @@ class control_logic(design.design): height=pin.height(), width=pin.width()) - + \ No newline at end of file diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index ac513c0e..12c12007 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -494,6 +494,7 @@ class hierarchical_decoder(design.design): result = result + z_t_decodeout_delay return result + def input_load(self): if self.determine_predecodes(self.num_inputs)[1]==0: pre = self.pre2_4 diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index c621b81e..5dbacf0e 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -55,5 +55,6 @@ class hierarchical_predecode2x4(hierarchical_predecode): return a_t_b_delay + b_t_z_delay + a_t_out_delay + def input_load(self): return self.nand.input_load() diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index eff12549..ded0c612 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -64,6 +64,5 @@ class hierarchical_predecode3x8(hierarchical_predecode): return a_t_b_delay + b_t_z_delay + a_t_out_delay - def input_load(self): return self.nand.input_load() diff --git a/compiler/modules/ms_flop.py b/compiler/modules/ms_flop.py index 01928790..e04b4246 100644 --- a/compiler/modules/ms_flop.py +++ b/compiler/modules/ms_flop.py @@ -26,4 +26,25 @@ class ms_flop(design.design): from tech import spice result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"]) return result + + def analytical_power(self, proc, vdd, temp, load): + """Returns dynamic and leakage power. Results in nW""" + from tech import spice + c_eff = self.calculate_effective_capacitance(load) + f = spice["default_event_rate"] + power_dyn = c_eff*vdd*vdd*f + power_leak = spice["msflop_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + from tech import spice, parameter + c_load = load + c_para = spice["flop_para_cap"]#ff + transistion_prob = spice["flop_transisition_prob"] + return transistion_prob*(c_load + c_para) + + \ No newline at end of file diff --git a/compiler/modules/ms_flop_array.py b/compiler/modules/ms_flop_array.py index ca51cda3..da3efc6d 100644 --- a/compiler/modules/ms_flop_array.py +++ b/compiler/modules/ms_flop_array.py @@ -134,3 +134,4 @@ class ms_flop_array(design.design): def analytical_delay(self, slew, load=0.0): return self.ms.analytical_delay(slew=slew, load=load) + diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py index fb6ddb6f..45a195fc 100644 --- a/compiler/modules/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -30,3 +30,8 @@ class sense_amp(design.design): result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) return self.return_delay(result.delay, result.slew) + def analytical_power(self, proc, vdd, temp, load): + """Returns dynamic and leakage power. Results in nW""" + #Power in this module currently not defined. Returns 0 nW (leakage and dynamic). + total_power = self.return_power() + return total_power diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 235a82c5..df40a38d 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -117,3 +117,4 @@ class sense_amp_array(design.design): def analytical_delay(self, slew, load=0.0): return self.amp.analytical_delay(slew=slew, load=load) + diff --git a/compiler/modules/tri_gate.py b/compiler/modules/tri_gate.py index 7351c575..cce7683c 100644 --- a/compiler/modules/tri_gate.py +++ b/compiler/modules/tri_gate.py @@ -32,7 +32,12 @@ class tri_gate(design.design): r = spice["min_tx_r"] c_para = spice["min_tx_drain_c"] return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) - + + def analytical_power(self, proc, vdd, temp, load): + """Returns dynamic and leakage power. Results in nW""" + #Power in this module currently not defined. Returns 0 nW (leakage and dynamic). + total_power = self.return_power() + return total_power def input_load(self): return 9*spice["min_tx_gate_c"] diff --git a/compiler/modules/tri_gate_array.py b/compiler/modules/tri_gate_array.py index fca72cf3..4bef69c2 100644 --- a/compiler/modules/tri_gate_array.py +++ b/compiler/modules/tri_gate_array.py @@ -111,3 +111,4 @@ class tri_gate_array(design.design): def analytical_delay(self, slew, load=0.0): return self.tri.analytical_delay(slew = slew, load = load) + diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index aaab96eb..67d414af 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -205,6 +205,7 @@ class wordline_driver(design.design): net_t_wl = self.inv.analytical_delay(decode_t_net.slew, load) return decode_t_net + net_t_wl - + + def input_load(self): return self.nand2.input_load() diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 8bcd7841..7bf71e5d 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -241,3 +241,20 @@ class pinv(pgate.pgate): r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"]) c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) + + def analytical_power(self, proc, vdd, temp, load): + """Returns dynamic and leakage power. Results in nW""" + c_eff = self.calculate_effective_capacitance(load) + freq = spice["default_event_rate"] + power_dyn = c_eff*vdd*vdd*freq + power_leak = spice["inv_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + c_load = load + c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff + transistion_prob = spice["inv_transisition_prob"] + return transistion_prob*(c_load + c_para) \ No newline at end of file diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index dfd89680..fa576850 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -213,3 +213,20 @@ class pnand2(pgate.pgate): r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"]) c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) + + def analytical_power(self, proc, vdd, temp, load): + """Returns dynamic and leakage power. Results in nW""" + c_eff = self.calculate_effective_capacitance(load) + freq = spice["default_event_rate"] + power_dyn = c_eff*vdd*vdd*freq + power_leak = spice["nand2_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + c_load = load + c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff + transistion_prob = spice["nand2_transisition_prob"] + return transistion_prob*(c_load + c_para) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 6d0b1e79..02262b39 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -233,3 +233,20 @@ class pnand3(pgate.pgate): r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"]) c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) + + def analytical_power(self, proc, vdd, temp, load): + """Returns dynamic and leakage power. Results in nW""" + c_eff = self.calculate_effective_capacitance(load) + freq = spice["default_event_rate"] + power_dyn = c_eff*vdd*vdd*freq + power_leak = spice["nand3_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + c_load = load + c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff + transistion_prob = spice["nand3_transisition_prob"] + return transistion_prob*(c_load + c_para) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 684a2b51..4ee1583e 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -223,3 +223,21 @@ class pnor2(pgate.pgate): r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"]) c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) + + def analytical_power(self, proc, vdd, temp, load): + """Returns dynamic and leakage power. Results in nW""" + c_eff = self.calculate_effective_capacitance(load) + freq = spice["default_event_rate"] + power_dyn = c_eff*vdd*vdd*freq + power_leak = spice["nor2_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + c_load = load + c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff + transistion_prob = spice["nor2_transisition_prob"] + return transistion_prob*(c_load + c_para) + \ No newline at end of file diff --git a/compiler/sram.py b/compiler/sram.py index 951a5ea3..74185aa2 100644 --- a/compiler/sram.py +++ b/compiler/sram.py @@ -1015,7 +1015,6 @@ class sram(design.design): """ LH and HL are the same in analytical model. """ return self.bank.analytical_delay(slew,load) - def save_output(self): """ Save all the output files while reporting time to do it as well. """ diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index 8a638a05..5143e33a 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -82,7 +82,7 @@ cell (sram_2_16_1_freepdk45){ leakage_power () { when : "CSb"; - value : 0; + value : 0.000173; } cell_leakage_power : 0; bus(DATA){ @@ -298,19 +298,19 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "!CSb & clk & !WEb"; rise_power(scalar){ - values("0.0"); + values("0.065526962224"); } fall_power(scalar){ - values("0.0"); + values("0.065526962224"); } } internal_power(){ when : "!CSb & !clk & WEb"; rise_power(scalar){ - values("0.0"); + values("0.065526962224"); } fall_power(scalar){ - values("0.0"); + values("0.065526962224"); } } internal_power(){ diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib index 8601c425..789f61a4 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib @@ -82,7 +82,7 @@ cell (sram_2_16_1_scn3me_subm){ leakage_power () { when : "CSb"; - value : 0; + value : 0.000173; } cell_leakage_power : 0; bus(DATA){ @@ -298,19 +298,19 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "!CSb & clk & !WEb"; rise_power(scalar){ - values("0.0"); + values("10.9314668117"); } fall_power(scalar){ - values("0.0"); + values("10.9314668117"); } } internal_power(){ when : "!CSb & !clk & WEb"; rise_power(scalar){ - values("0.0"); + values("10.9314668117"); } fall_power(scalar){ - values("0.0"); + values("10.9314668117"); } } internal_power(){ diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index ab2de4de..8207d373 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -113,19 +113,8 @@ def write_netgen_script(cell_name, sp_name): f = open(run_file, "w") f.write("#!/bin/sh\n") f.write("{} -noconsole << EOF\n".format(OPTS.lvs_exe[1])) - f.write("readnet spice {}.spice\n".format(cell_name)) - f.write("readnet spice {}\n".format(sp_name)) - f.write("ignore class c\n") - f.write("permute transistors\n") - f.write("equate class {{{0}.spice nfet}} {{{1} n}}\n".format(cell_name, sp_name)) - f.write("equate class {{{0}.spice pfet}} {{{1} p}}\n".format(cell_name, sp_name)) - # This circuit has symmetries and needs to be flattened to resolve them or the banks won't pass - # Is there a more elegant way to add this when needed? - f.write("flatten class {{{0}.spice precharge_array}}\n".format(cell_name)) - f.write("property {{{0}.spice nfet}} remove as ad ps pd\n".format(cell_name)) - f.write("property {{{0}.spice pfet}} remove as ad ps pd\n".format(cell_name)) - f.write("property {{{0} n}} remove as ad ps pd\n".format(sp_name)) - f.write("property {{{0} p}} remove as ad ps pd\n".format(sp_name)) + f.write("readnet spice {0}.spice\n".format(cell_name)) + f.write("readnet spice {0}\n".format(sp_name)) # Allow some flexibility in W size because magic will snap to a lambda grid # This can also cause disconnects unfortunately! # f.write("property {{{0}{1}.spice nfet}} tolerance {{w 0.1}}\n".format(OPTS.openram_temp, @@ -137,6 +126,24 @@ def write_netgen_script(cell_name, sp_name): f.write("EOF\n") f.close() os.system("chmod u+x {}".format(run_file)) + + setup_file = OPTS.openram_temp + "setup.tcl" + f = open(setup_file, "w") + f.write("ignore class c\n") + f.write("equate class {{nfet {0}.spice}} {{n {1}}}\n".format(cell_name, sp_name)) + f.write("equate class {{pfet {0}.spice}} {{p {1}}}\n".format(cell_name, sp_name)) + # This circuit has symmetries and needs to be flattened to resolve them or the banks won't pass + # Is there a more elegant way to add this when needed? + f.write("flatten class {{{0}.spice precharge_array}}\n".format(cell_name)) + f.write("property {{nfet {0}.spice}} remove as ad ps pd\n".format(cell_name)) + f.write("property {{pfet {0}.spice}} remove as ad ps pd\n".format(cell_name)) + f.write("property {{n {0}}} remove as ad ps pd\n".format(sp_name)) + f.write("property {{p {0}}} remove as ad ps pd\n".format(sp_name)) + f.write("permute transistors\n") + f.write("permute pins n source drain\n") + f.write("permute pins p source drain\n") + f.close() + def run_drc(cell_name, gds_name, extract=False): """Run DRC check on a cell which is implemented in gds_name.""" diff --git a/technology/freepdk45/sp_lib/ms_flop.sp b/technology/freepdk45/sp_lib/ms_flop.sp index e1967d84..03016e5d 100644 --- a/technology/freepdk45/sp_lib/ms_flop.sp +++ b/technology/freepdk45/sp_lib/ms_flop.sp @@ -1,10 +1,5 @@ *master-slave flip-flop with both output and inverted ouput -.SUBCKT ms_flop din dout dout_bar clk vdd gnd -xmaster din mout mout_bar clk clk_bar vdd gnd dlatch -xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch -.ENDS flop - .SUBCKT dlatch din dout dout_bar clk clk_bar vdd gnd *clk inverter mPff1 clk_bar clk vdd vdd PMOS_VTG W=180.0n L=50n m=1 @@ -27,3 +22,8 @@ mtmP2 int1 clk_bar dout vdd PMOS_VTG W=180.0n L=50n m=1 mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1 .ENDS dlatch +.SUBCKT ms_flop din dout dout_bar clk vdd gnd +xmaster din mout mout_bar clk clk_bar vdd gnd dlatch +xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch +.ENDS flop + diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index e98d78f3..528c6978 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -283,6 +283,21 @@ spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load spice["dff_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad] +# analytical power parameters, many values are temporary +spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW +spice["inv_leakage"] = 1 # Leakage power of inverter in nW +spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW +spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW +spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW +spice["msflop_leakage"] = 1 # Leakage power of flop in nW +spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF + +spice["default_event_rate"] = 100 # Default event activity of every gate. MHz +spice["flop_transisition_prob"] = .5 # Transition probability of inverter. +spice["inv_transisition_prob"] = .5 # Transition probability of inverter. +spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand. +spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand. +spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor. ################################################### ##END Spice Simulation Parameters diff --git a/technology/freepdk45/tf/APACHE-LICENSE-2.0.txt b/technology/freepdk45/tf/APACHE-LICENSE-2.0.txt new file mode 100644 index 00000000..2bb9ad24 --- /dev/null +++ b/technology/freepdk45/tf/APACHE-LICENSE-2.0.txt @@ -0,0 +1,176 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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blockage metal10 t nil t t nil ) + ( contact drawing contact t t t t t ) + ( contact blockage contact t nil t t nil ) + ( via1 drawing via1 t t t t t ) + ( via1 blockage via1 t nil t t nil ) + ( via2 drawing via2 t t t t t ) + ( via2 blockage via2 t nil t t nil ) + ( via3 drawing via3 t t t t t ) + ( via3 blockage via3 t nil t t nil ) + ( via4 drawing via4 t t t t t ) + ( via4 blockage via4 t nil t t nil ) + ( via5 drawing via5 t t t t t ) + ( via5 blockage via5 t nil t t nil ) + ( via6 drawing via6 t t t t t ) + ( via6 blockage via6 t nil t t nil ) + ( via7 drawing via7 t t t t t ) + ( via7 blockage via7 t nil t t nil ) + ( via8 drawing via8 t t t t t ) + ( via8 blockage via8 t nil t t nil ) + ( via9 drawing via9 t t t t t ) + ( via9 blockage via9 t nil t t nil ) + ( background drawing background t nil t nil nil ) + ( grid drawing grid t nil t nil nil ) + ( grid drawing1 grid1 t nil t nil nil ) + ( annotate drawing annotate t t t t nil ) + ( annotate drawing1 annotate1 t t t t nil ) + ( annotate drawing2 annotate2 t t t t nil ) + ( annotate drawing3 annotate3 t t t t nil ) + ( annotate drawing4 annotate4 t t t t nil ) + ( annotate drawing5 annotate5 t t t t nil ) + ( annotate drawing6 annotate6 t t t t nil ) + ( annotate drawing7 annotate7 t t t t nil ) + ( annotate drawing8 annotate8 t t t t nil ) + ( annotate drawing9 annotate9 nil t t t nil ) + ( instance drawing instance t t t t nil ) + ( instance label instanceLbl t t t t nil ) + ( prBoundary drawing prBoundary t t t t nil ) + ( prBoundary boundary prBoundaryBnd t t t t nil ) + ( prBoundary label prBoundaryLbl t t t t nil ) + ( align drawing align t t t t nil ) + ( hardFence drawing hardFence t t t t nil ) + ( softFence drawing softFence t t t t nil ) + ( text drawing text t t t t t ) + ( text drawing1 text1 t t t t nil ) + ( text drawing2 text2 t t t t nil ) + ( border drawing border t t t t nil ) + ( device drawing device t t t t nil ) + ( device label deviceLbl t t t t nil ) + ( device drawing1 device1 t t t t nil ) + ( device drawing2 device2 t t t t nil ) + ( device annotate deviceAnt t t t t nil ) + ( wire drawing wire t t t t nil ) + ( wire label wireLbl t t t t nil ) + ( wire flight wireFlt t t t t nil ) + ( pin label pinLbl t t t t nil ) + ( pin drawing pin t t t t nil ) + ( pin annotate pinAnt t t t t nil ) + ( axis drawing axis t nil t t nil ) + ( edgeLayer drawing edgeLayer t t t t nil ) + ( edgeLayer pin edgeLayerPin t t t t nil ) + ( snap drawing snap t t t t nil ) + ( stretch drawing stretch t t t t nil ) + ( y0 drawing y0 t t t t nil ) + ( y1 drawing y1 t t t t nil ) + ( y2 drawing y2 t t t t nil ) + ( y3 drawing y3 t t t t nil ) + ( y4 drawing y4 t t t t nil ) + ( y5 drawing y5 t t t t nil ) + ( y6 drawing y6 t t t t nil ) + ( y7 drawing y7 t t t t nil ) + ( y8 drawing y8 t t t t nil ) + ( y9 drawing y9 t t t t nil ) + ( hilite drawing hilite t t t t nil ) + ( hilite drawing1 hilite1 t t t t nil ) + ( hilite drawing2 hilite2 t t t t nil ) + ( hilite drawing3 hilite3 t t t t nil ) + ( hilite drawing4 hilite4 t t t t nil ) + ( hilite drawing5 hilite5 t t t t nil ) + ( hilite drawing6 hilite6 t t t t nil ) + ( hilite drawing7 hilite7 t t t t nil ) + ( hilite drawing8 hilite8 t t t t nil ) + ( hilite drawing9 hilite9 t t t t nil ) + ( select drawing select t t t t nil ) + ( drive drawing drive t t t t nil ) + ( hiz drawing hiz t t t t nil ) + ( resist drawing resist t t t t nil ) + ( spike drawing spike t t t t nil ) + ( supply drawing supply t t t t nil ) + ( unknown drawing unknown t t t t nil ) + ( unset drawing unset t t t t nil ) + ( designFlow drawing designFlow t t t nil nil ) + ( designFlow drawing1 designFlow1 t t t nil nil ) + ( designFlow drawing2 designFlow2 t t t nil nil ) + ( designFlow drawing3 designFlow3 t t t nil nil ) + ( designFlow drawing4 designFlow4 t t t nil nil ) + ( designFlow drawing5 designFlow5 t t t nil nil ) + ( designFlow drawing6 designFlow6 t t t nil nil ) + ( designFlow drawing7 designFlow7 t t t nil nil ) + ( designFlow drawing8 designFlow8 t t t nil nil ) + ( designFlow drawing9 designFlow9 t t t nil nil ) + ( changedLayer tool0 changedLayerTl0 nil nil t nil nil ) + ( changedLayer tool1 changedLayerTl1 nil nil t nil nil ) + ( marker warning markerWarn t t t t nil ) + ( marker error markerErr t t t t nil ) + ( Row drawing Row t t t t nil ) + ( Row label RowLbl t nil t t nil ) + ( Group drawing Group t t t t nil ) + ( Group label GroupLbl t nil t t nil ) + ( contact label contactLbl t t t nil nil ) + ( metal1 label metal1Lbl t t t nil nil ) + ( metal2 label metal2Lbl t t t nil nil ) + ( metal3 label metal3Lbl t t t nil nil ) + ( metal4 label metal4Lbl t t t nil nil ) + ( metal5 label metal5Lbl t t t nil nil ) + ( metal6 label metal6Lbl t t t nil nil ) + ( metal7 label metal7Lbl t t t nil nil ) + ( metal8 label metal8Lbl t t t nil nil ) + ( metal9 label metal9Lbl t t t nil nil ) + ( metal10 label metal10Lbl t t t nil nil ) + ( poly label polyLbl t t t nil nil ) + ( thkox label thkoxLbl t t t nil nil ) + ( via1 label via1Lbl t t t nil nil ) + ( via2 label via2Lbl t t t nil nil ) + ( via3 label via3Lbl t t t nil nil ) + ( via4 label via4Lbl t t t nil nil ) + ( via5 label via5Lbl t t t nil nil ) + ( via6 label via6Lbl t t t nil nil ) + ( via7 label via7Lbl t t t nil nil ) + ( via8 label via8Lbl t t t nil nil ) + ( via9 label via9Lbl t t t nil nil ) + ( pwell net pwellNet t t t nil t ) + ( nwell net nwellNet t t t nil t ) + ( vtg net vtgNet t t t nil t ) + ( vth net vthNet t t t nil t ) + ( active net activeNet t t t nil t ) + ( poly net polyNet t t t nil t ) + ( metal1 net metal1Net t t t nil t ) + ( metal2 net metal2Net t t t nil t ) + ( metal3 net metal3Net t t t nil t ) + ( metal4 net metal4Net t t t nil t ) + ( metal5 net metal5Net t t t nil t ) + ( metal6 net metal6Net t t t nil t ) + ( metal7 net metal7Net t t t nil t ) + ( metal8 net metal8Net t t t nil t ) + ( metal9 net metal9Net t t t nil t ) + ( metal10 net metal10Net t t t nil t ) + ( contact net contactNet t t t nil t ) + ( via1 net via1Net t t t nil t ) + ( via2 net via2Net t t t nil t ) + ( via3 net via3Net t t t nil t ) + ( via4 net via4Net t t t nil t ) + ( via5 net via5Net t t t nil t ) + ( via6 net via6Net t t t nil t ) + ( via7 net via7Net t t t nil t ) + ( via8 net via8Net t t t nil t ) + ( via9 net via9Net t t t nil t ) + ( active pin activePin t t t nil nil ) + ( contact pin contactPin t t t nil nil ) + ( metal1 pin metal1Pin t t t nil nil ) + ( metal2 pin metal2Pin t t t nil nil ) + ( metal3 pin metal3Pin t t t nil nil ) + ( metal4 pin metal4Pin t t t nil nil ) + ( metal5 pin metal5Pin t t t nil nil ) + ( metal6 pin metal6Pin t t t nil nil ) + ( metal7 pin metal7Pin t t t nil nil ) + ( metal8 pin metal8Pin t t t nil nil ) + ( metal9 pin metal9Pin t t t nil nil ) + ( metal10 pin metal10Pin t t t nil nil ) + ( nwell pin nwellPin t t t nil nil ) + ( poly pin polyPin t t t nil nil ) + ( pwell pin pwellPin t t t nil nil ) + ( via1 pin via1Pin t t t nil nil ) + ( via2 pin via2Pin t t t nil nil ) + ( via3 pin via3Pin t t t nil nil ) + ( via4 pin via4Pin t t t nil nil ) + ( via5 pin via5Pin t t t nil nil ) + ( via6 pin via6Pin t t t nil nil ) + ( via7 pin via7Pin t t t nil nil ) + ( via8 pin via8Pin t t t nil nil ) + ( via9 pin via9Pin t t t nil nil ) + ( Cannotoccupy drawing Cannotoccupy t t t t nil ) + ( Cannotoccupy boundary CannotoccupyBnd t t t t nil ) + ( Canplace drawing Canplace t t t t nil ) + ( contact boundary contactBnd t t t nil nil ) + ( metal1 boundary metal1Bnd t t t nil nil ) + ( metal2 boundary metal2Bnd t t t nil nil ) + ( metal3 boundary metal3Bnd t t t nil nil ) + ( metal4 boundary metal4Bnd t t t nil nil ) + ( metal5 boundary metal5Bnd t t t nil nil ) + ( metal6 boundary metal6Bnd t t t nil nil ) + ( metal7 boundary metal7Bnd t t t nil nil ) + ( metal8 boundary metal8Bnd t t t nil nil ) + ( metal9 boundary metal9Bnd t t t nil nil ) + ( metal10 boundary metal10Bnd t t t nil nil ) + ( poly boundary polyBnd t t t nil nil ) + ( via1 boundary via1Bnd t t t nil nil ) + ( via2 boundary via2Bnd t t t nil nil ) + ( via3 boundary via3Bnd t t t nil nil ) + ( via4 boundary via4Bnd t t t nil nil ) + ( via5 boundary via5Bnd t t t nil nil ) + ( via6 boundary via6Bnd t t t nil nil ) + ( via7 boundary via7Bnd t t t nil nil ) + ( via8 boundary via8Bnd t t t nil nil ) + ( via9 boundary via9Bnd t t t nil nil ) + ( Unrouted drawing Unrouted t t t t nil ) + ( Unrouted drawing1 Unrouted1 t t t t nil ) + ( Unrouted drawing2 Unrouted2 t t t t nil ) + ( Unrouted drawing3 Unrouted3 t t t t nil ) + ( Unrouted drawing4 Unrouted4 t t t t nil ) + ( Unrouted drawing5 Unrouted5 t t t t nil ) + ( Unrouted drawing6 Unrouted6 t t t t nil ) + ( Unrouted drawing7 Unrouted7 t t t t nil ) + ( Unrouted drawing8 Unrouted8 t t t t nil ) + ( Unrouted drawing9 Unrouted9 t t t t nil ) + ( snap boundary snap t nil t t nil ) + ( Row boundary RowBnd t t t t nil ) + ( Unrouted track UnroutedTrk t t t t nil ) + ( marker annotate markerAno t t t t nil ) + ( marker info markerInf t t t t nil ) + ( marker ackWarn markerAck t t t t nil ) + ( marker soError markerSer t t t t nil ) + ( marker soCritical markerScr t t t t nil ) + ( marker critical markerCrt t t t t nil ) + ( marker fatal markerFat t t t t nil ) + ( Group boundary GroupBnd t nil t t nil ) + ( y0 flight y0Flt t t t t nil ) + ( y1 flight y1Flt t t t t nil ) + ( y2 flight y2Flt t t t t nil ) + ( y3 flight y3Flt t t t t nil ) + ( y4 flight y4Flt t t t t nil ) + ( y5 flight y5Flt t t t t nil ) + ( y6 flight y6Flt t t t t nil ) + ( y7 flight y7Flt t t t t nil ) + ( y8 flight y8Flt t t t t nil ) + ( y9 flight y9Flt t t t t nil ) + ( border boundary area t nil t t nil ) + ) ;techDisplays + + techLayerProperties( + ;( PropName Layer1 [ Layer2 ] PropValue ) + ;( -------- ------ ---------- --------- ) + ( contactResistance via2 11.390000 ) + ( contactResistance via1 5.690000 ) + ( contactResistance via3 16.730000 ) + ( contactResistance via4 21.440000 ) + ( contactResistance via5 24.080000 ) + ( contactResistance via6 11.390000 ) + ( contactResistance via7 5.690000 ) + ( contactResistance via8 16.730000 ) + ( contactResistance via9 21.440000 ) + ( sheetResistance nwell 933.000000 ) + ( sheetResistance poly 7.800000 ) + ( sheetResistance metal1 0.380000 ) + ( sheetResistance metal3 0.250000 ) + ( sheetResistance metal4 0.250000 ) + ( sheetResistance metal5 0.250000 ) + ( sheetResistance metal6 0.250000 ) + ( sheetResistance metal2 0.250000 ) + ( sheetResistance metal7 0.250000 ) + ( sheetResistance metal8 0.250000 ) + ( sheetResistance metal9 0.210000 ) + ( sheetResistance metal10 0.210000 ) + ( contactResistance contact 10.500000 ) + ( areaCap active metal1 51 ) + ( areaCap active metal3 13 ) + ( areaCap active metal4 10 ) + ( areaCap active metal5 9 ) + ( areaCap active metal6 8 ) + ( areaCap active metal2 19 ) + ( areaCap active metal7 51 ) + ( areaCap active metal8 13 ) + ( areaCap active metal9 10 ) + ( areaCap active metal10 9 ) + ( areaCap poly metal1 61 ) + ( areaCap poly metal3 9 ) + ( areaCap poly metal4 7 ) + ( areaCap poly metal5 5 ) + ( areaCap poly metal6 4 ) + ( areaCap poly metal2 16 ) + ( areaCap poly metal7 61 ) + ( areaCap poly metal8 9 ) + ( areaCap poly metal9 7 ) + ( areaCap poly metal10 5 ) + ( perimeterCap poly metal1 66 ) + ( perimeterCap poly metal3 28 ) + ( perimeterCap poly metal4 23 ) + ( perimeterCap poly metal5 19 ) + ( perimeterCap poly metal6 17 ) + ( perimeterCap poly metal2 38 ) + ( perimeterCap poly metal7 66 ) + ( perimeterCap poly metal8 28 ) + ( perimeterCap poly metal9 23 ) + ( perimeterCap poly metal10 19 ) + ( areaCap metal1 metal3 13 ) + ( areaCap metal1 metal4 9 ) + ( areaCap metal1 metal5 6 ) + ( areaCap metal1 metal6 5 ) + ( areaCap metal1 metal2 34 ) + ( areaCap metal1 metal7 13 ) + ( areaCap metal1 metal8 9 ) + ( areaCap metal1 metal9 6 ) + ( areaCap metal1 metal10 5 ) + ( perimeterCap metal1 metal3 34 ) + ( perimeterCap metal1 metal4 34 ) + ( perimeterCap metal1 metal5 21 ) + ( perimeterCap metal1 metal6 18 ) + ( perimeterCap metal1 metal2 49 ) + ( perimeterCap metal1 metal7 49 ) + ( perimeterCap metal1 metal8 34 ) + ( perimeterCap metal1 metal9 34 ) + ( perimeterCap metal1 metal10 21 ) + ( areaCap metal3 metal2 36 ) + ( areaCap metal3 metal4 34 ) + ( areaCap metal3 metal5 14 ) + ( areaCap metal3 metal6 8 ) + ( areaCap metal3 metal7 36 ) + ( areaCap metal3 metal8 34 ) + ( areaCap metal3 metal9 14 ) + ( areaCap metal3 metal10 8 ) + ( perimeterCap metal3 metal2 46 ) + ( perimeterCap metal3 metal4 52 ) + ( perimeterCap metal3 metal5 34 ) + ( perimeterCap metal3 metal6 27 ) + ( perimeterCap metal3 metal7 46 ) + ( perimeterCap metal3 metal8 52 ) + ( perimeterCap metal3 metal9 34 ) + ( perimeterCap metal3 metal10 27 ) + ( areaCap metal4 metal2 13 ) + ( areaCap metal4 metal5 36 ) + ( areaCap metal4 metal6 13 ) + ( areaCap metal4 metal7 13 ) + ( areaCap metal4 metal8 36 ) + ( areaCap metal4 metal9 13 ) + ( areaCap metal4 metal10 13 ) + ( perimeterCap metal4 metal2 45 ) + ( perimeterCap metal4 metal5 57 ) + ( perimeterCap metal4 metal6 34 ) + ( perimeterCap metal4 metal7 45 ) + ( perimeterCap metal4 metal8 57 ) + ( perimeterCap metal4 metal9 34 ) + ( perimeterCap metal4 metal10 45 ) + ( areaCap metal5 metal2 8 ) + ( areaCap metal5 metal6 33 ) + ( areaCap metal5 metal7 33 ) + ( areaCap metal5 metal8 33 ) + ( areaCap metal5 metal9 33 ) + ( areaCap metal5 metal10 33 ) + ( perimeterCap metal5 metal2 26 ) + ( perimeterCap metal5 metal6 47 ) + ( perimeterCap metal5 metal7 47 ) + ( perimeterCap metal5 metal8 47 ) + ( perimeterCap metal5 metal9 47 ) + ( perimeterCap metal5 metal10 47 ) + ( areaCap metal6 metal2 6 ) + ( areaCap metal6 metal7 6 ) + ( areaCap metal6 metal8 6 ) + ( areaCap metal6 metal9 6 ) + ( areaCap metal6 metal10 6 ) + ( perimeterCap metal6 metal2 22 ) + ( perimeterCap metal6 metal7 22 ) + ( perimeterCap metal6 metal8 22 ) + ( perimeterCap metal6 metal9 22 ) + ( perimeterCap metal6 metal10 22 ) + ( areaCap metal7 metal2 6 ) + ( areaCap metal7 metal8 6 ) + ( areaCap metal7 metal9 6 ) + ( areaCap metal7 metal10 6 ) + ( perimeterCap metal7 metal2 22 ) + ( perimeterCap metal7 metal8 22 ) + ( perimeterCap metal7 metal9 22 ) + ( perimeterCap metal7 metal10 22 ) + ( areaCap metal8 metal2 6 ) + ( areaCap metal8 metal9 6 ) + ( areaCap metal8 metal10 6 ) + ( perimeterCap metal8 metal2 22 ) + ( perimeterCap metal8 metal9 22 ) + ( perimeterCap metal8 metal10 22 ) + ( areaCap metal9 metal2 6 ) + ( areaCap metal9 metal10 6 ) + ( perimeterCap metal9 metal2 22 ) + ( perimeterCap metal9 metal10 22 ) + ( areaCap metal10 metal2 6 ) + ( perimeterCap metal10 metal2 22 ) + ) ;techLayerProperties + + techDerivedLayers( + ;( DerivedLayerName # composition ) + ;( ---------------- ------ ------------ ) + ( noOverlapLayer1 10001 ( poly 'and active )) + ( noOverlapLayer2 10002 ( via1 'and contact )) + ) ;techDerivedLayers + +) ;layerDefinitions + + +;******************************** +; LAYER RULES +;******************************** +layerRules( + + equivalentLayers( + ;( list of layers ) + ;( -------------- ) + ) ;equivalentLayers + + functions( + ;( layer function [maskNumber]) + ;( ----- -------- ------------) + ( active "unknown" 1 ) + ( poly "poly" 9 ) + ( contact "cut" 10 ) + ( metal1 "metal" 11 ) + ( via1 "cut" 12 ) + ( metal2 "metal" 13 ) + ( via2 "cut" 14 ) + ( metal3 "metal" 15 ) + ( via3 "cut" 16 ) + ( metal4 "metal" 17 ) + ( via4 "cut" 18 ) + ( metal5 "metal" 19 ) + ( via5 "cut" 20 ) + ( metal6 "metal" 21 ) + ( via6 "cut" 22 ) + ( metal7 "metal" 23 ) + ( via7 "cut" 24 ) + ( metal8 "metal" 25 ) + ( via8 "cut" 26 ) + ( metal9 "metal" 27 ) + ( via9 "cut" 28 ) + ( metal10 "metal" 29 ) + ) ;functions + + routingDirections( + ;( layer direction ) + ;( ----- --------- ) + ( metal1 "horizontal" ) + ( metal10 "vertical" ) + ( metal2 "vertical" ) + ( metal3 "horizontal" ) + ( metal4 "vertical" ) + ( metal5 "horizontal" ) + ( metal6 "vertical" ) + ( metal7 "horizontal" ) + ( metal8 "vertical" ) + ( metal9 "horizontal" ) + ) ;routingDirections + + currentDensity( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ) ;currentDensity + + currentDensityTables( + ;( rule layer1 + ; (( index1Definitions [index2Definitions]) [defaultValue] ) + ; (table)) + ;( ----------------------------------------------------------------------) + ) ;currentDensityTables + +) ;layerRules + + +;******************************** +; VIADEFS +;******************************** +viaDefs( + + standardViaDefs( + ;( viaDefName layer1 layer2 (cutLayer cutWidth cutHeight [resistancePerCut]) + ; (cutRows cutCol (cutSpace)) + ; (layer1Enc) (layer2Enc) (layer1Offset) (layer2Offset) (origOffset) + ; [implant1 (implant1Enc) [implant2 (implant2Enc)]]) + ;( -------------------------------------------------------------------------- ) + ( M2_M1 metal1 metal2 ("via1" 0.065 0.065) + (1 1 (0.075 0.075)) + (0.0 0.035) (0.0 0.035) (0.0 0.0) (0.0 0.0) (0.0 0.0) + ) + ( M3_M2 metal2 metal3 ("via2" 0.07 0.07) + (1 1 (0.085 0.085)) + (0.0 0.035) (0.0 0.035) (0.0 0.0) (0.0 0.0) (0.0 0.0) + ) + ( M4_M3 metal3 metal4 ("via3" 0.07 0.07) + (1 1 (0.085 0.085)) + (0.0 0.035) (0.0 0.0) (0.0 0.0) (0.0 0.0) (0.0 0.0) + ) + ( M5_M4 metal4 metal5 ("via4" 0.14 0.14) + (1 1 (0.16 0.16)) + (0.0 0.0) (0.0 0.0) (0.0 0.0) (0.0 0.0) (0.0 0.0) + ) + ( M6_M5 metal5 metal6 ("via5" 0.14 0.14) + (1 1 (0.16 0.16)) + (0.0 0.0) (0.0 0.0) (0.0 0.0) (0.0 0.0) (0.0 0.0) + ) + ( M7_M6 metal6 metal7 ("via6" 0.14 0.14) + (1 1 (0.16 0.16)) + (0.0 0.0) (0.13 0.13) (0.0 0.0) (0.0 0.0) (0.0 0.0) + ) + ( M8_M7 metal7 metal8 ("via7" 0.4 0.4) + (1 1 (0.4 0.4)) + (0.0 0.0) (0.0 0.0) (0.0 0.0) (0.0 0.0) (0.0 0.0) + ) + ( M9_M8 metal8 metal9 ("via8" 0.4 0.4) + (1 1 (0.4 0.4)) + (0.0 0.0) (0.2 0.2) (0.0 0.0) (0.0 0.0) (0.0 0.0) + ) + ( M10_M9 metal9 metal10 ("via9" 0.8 0.8) + (1 1 (0.8 0.8)) + (0.0 0.0) (0.0 0.0) (0.0 0.0) (0.0 0.0) (0.0 0.0) + ) + ( M1_POLY poly metal1 ("contact" 0.065 0.065) + (1 1 (0.075 0.075)) + (0.0 0.0) (0.0 0.035) (0.0 0.0) (0.0 0.0) (0.0 0.0) + ) + ( NTAP nwell metal1 ("contact" 0.065 0.065) + (1 1 (0.075 0.075)) + (0.0675 0.0675) (0.0 0.035) (0.0 0.0) (0.0 0.0) (0.0 0.0) + nimplant (-0.055 -0.055) active (0.0125 -0.0225) + ) + ( PTAP pwell metal1 ("contact" 0.065 0.065) + (1 1 (0.075 0.075)) + (0.0675 0.0675) (0.0 0.035) (0.0 0.0) (0.0 0.0) (0.0 0.0) + pimplant (-0.055 -0.055) active (0.0125 -0.0225) + ) + ( M1_N active metal1 ("contact" 0.065 0.065) + (1 1 (0.075 0.075)) + (0.005 0.005) (0.0 0.035) (0.0 0.0) (0.0 0.0) (0.0 0.0) + nimplant (0.0 0.0) + ) + ( M1_P active metal1 ("contact" 0.065 0.065) + (1 1 (0.075 0.075)) + (0.005 0.005) (0.0 0.035) (0.0 0.0) (0.0 0.0) (0.0 0.0) + pimplant (0.0 0.0) + ) + ) ;standardViaDefs + + customViaDefs( + ;( viaDefName libName cellName viewName layer1 layer2 resistancePerCut) + ;( ---------- ------- -------- -------- ------ ------ ----------------) + ( M2_M1_via NCSU_TechLib_FreePDK45 M2_M1_via via metal1 metal2 0.0) + ( M3_M2_via NCSU_TechLib_FreePDK45 M3_M2_via via metal2 metal3 0.0) + ( M4_M3_via NCSU_TechLib_FreePDK45 M4_M3_via via metal3 metal4 0.0) + ( M5_M4_via NCSU_TechLib_FreePDK45 M5_M4_via via metal4 metal5 0.0) + ( M6_M5_via NCSU_TechLib_FreePDK45 M6_M5_via via metal5 metal6 0.0) + ( M7_M6_via NCSU_TechLib_FreePDK45 M7_M6_via via metal6 metal7 0.0) + ( M8_M7_via NCSU_TechLib_FreePDK45 M8_M7_via via metal7 metal8 0.0) + ( M9_M8_via NCSU_TechLib_FreePDK45 M9_M8_via via metal8 metal9 0.0) + ( M10_M9_via NCSU_TechLib_FreePDK45 M10_M9_via via metal9 metal10 0.0) + ( M2_M1_viaB NCSU_TechLib_FreePDK45 M2_M1_viaB via metal1 metal2 0.0) + ( M2_M1_viaC NCSU_TechLib_FreePDK45 M2_M1_viaC via metal1 metal2 0.0) + ( M3_M2_viaB NCSU_TechLib_FreePDK45 M3_M2_viaB via metal2 metal3 0.0) + ( M3_M2_viaC NCSU_TechLib_FreePDK45 M3_M2_viaC via metal2 metal3 0.0) + ( M4_M3_viaB NCSU_TechLib_FreePDK45 M4_M3_viaB via metal3 metal4 0.0) + ) ;customViaDefs + +) ;viaDefs + + + +;******************************** +; CONSTRAINT GROUPS +;******************************** +constraintGroups( + + ;( group [override] ) + ;( ----- ---------- ) + ( "virtuosoDefaultExtractorSetup" nil + + interconnect( + ( validLayers (metal10 metal9 metal8 metal7 metal6 metal5 metal4 metal3 metal2 metal1 via9 via8 via7 via6 via5 via4 via3 via2 via1 contact poly active nwell pwell ) ) + ( errorLayer noOverlapLayer1 ) + ( errorLayer noOverlapLayer2 ) + ) ;interconnect + ) ;virtuosoDefaultExtractorSetup + + ;( group [override] ) + ;( ----- ---------- ) + ( "LEFDefaultRouteSpec" nil + + interconnect( + ( validLayers (metal1 metal2 metal3 metal4 metal5 metal6 metal7 metal8 metal9 metal10 ) ) + ) ;interconnect + + routingGrids( + ( horizontalPitch "metal1" 0.19 ) + ( verticalPitch "metal1" 0.19 ) + ( horizontalPitch "metal2" 0.19 ) + ( verticalPitch "metal2" 0.19 ) + ( horizontalPitch "metal3" 0.19 ) + ( verticalPitch "metal3" 0.19 ) + ( horizontalPitch "metal4" 0.285 ) + ( verticalPitch "metal4" 0.285 ) + ( horizontalPitch "metal5" 0.285 ) + ( verticalPitch "metal5" 0.285 ) + ( horizontalPitch "metal6" 0.285 ) + ( verticalPitch "metal6" 0.285 ) + ( horizontalPitch "metal7" 0.855 ) + ( verticalPitch "metal7" 0.855 ) + ( horizontalPitch "metal8" 0.855 ) + ( verticalPitch "metal8" 0.855 ) + ( horizontalPitch "metal9" 1.71 ) + ( verticalPitch "metal9" 1.71 ) + ( horizontalPitch "metal10" 1.71 ) + ( verticalPitch "metal10" 1.71 ) + ) ;routingGrids + + interconnect( + ( validVias (M2_M1_via M3_M2_via M4_M3_via M5_M4_via M6_M5_via M7_M6_via M8_M7_via M9_M8_via M10_M9_via M2_M1_viaB M2_M1_viaC M3_M2_viaB M3_M2_viaC M4_M3_viaB ) ) + ) ;interconnect + ) ;LEFDefaultRouteSpec + + ;( group [override] ) + ;( ----- ---------- ) + ( "foundry" nil + + orderedSpacings( + ( minEnclosure "nimplant" "active" 0.0 ) + ( minEnclosure "pimplant" "active" 0.0 ) + ( minEnclosure "nwell" "active" 0.055 ) + ( minEnclosure "pwell" "active" 0.055 ) + ( minEnclosure "nimplant" "contact" 0.005 ) + ( minEnclosure "pimplant" "contact" 0.005 ) + ( minEnclosure "active" "contact" 0.005 ) + ( minEnclosure "poly" "contact" 0.005 ) + ( minEnclosure "metal1" "contact" 0.0 ) + ( minEnclosure "metal1" "via1" 0.0 ) + ( minEnclosure "metal2" "via1" 0.0 ) + ( minEnclosure "nwell" "active" 0.0 ) + ( minEnclosure "pwell" "active" 0.0 ) + ( minEnclosure "metal2" "via2" 0.0 ) + ( minEnclosure "metal3" "via2" 0.0 ) + ( minEnclosure "metal3" "via3" 0.0 ) + ( minEnclosure "metal4" "via3" 0.0 ) + ( minEnclosure "metal4" "via4" 0.0 ) + ( minEnclosure "metal5" "via4" 0.0 ) + ( minEnclosure "metal5" "via5" 0.0 ) + ( minEnclosure "metal6" "via5" 0.0 ) + ( minEnclosure "metal6" "via6" 0.0 ) + ( minEnclosure "metal7" "via6" 0.0 ) + ( minEnclosure "metal7" "via7" 0.0 ) + ( minEnclosure "metal8" "via7" 0.0 ) + ( minEnclosure "metal8" "via8" 0.0 ) + ( minEnclosure "metal9" "via8" 0.0 ) + ( minEnclosure "metal9" "via9" 0.0 ) + ( minEnclosure "metal10" "via9" 0.0 ) + ) ;orderedSpacings + + spacings( + ( minSameNetSpacing "nwell" 0.135 ) + ( minSpacing "nwell" "active" 0.055 ) + ( minSpacing "pwell" "active" 0.055 ) + ( minSameNetSpacing "pwell" 0.135 ) + ( minSpacing "active" 0.08 ) + ( minSameNetSpacing "active" 0.08 ) + ( minWidth "active" 0.09 ) + ( minSpacing "nimplant" 0.045 ) + ( minSpacing "pimplant" 0.045 ) + ( minSameNetSpacing "nimplant" 0.045 ) + ( minSameNetSpacing "pimplant" 0.045 ) + ( minWidth "nimplant" 0.045 ) + ( minWidth "pimplant" 0.045 ) + ( minWidth "poly" 0.05 ) + ( minSpacing "poly" "contact" 0.09 ) + ( minSpacing "metal1" 0.065 ) + ( minSameNetSpacing "metal1" 0.065 ) + ( minWidth "metal1" 0.065 ) + ( minWidth "metal2" 0.070 ) + ( minSpacing "via1" 0.075 ) + ( minWidth "via1" 0.065 ) + ( minSpacing "metal2" 0.075 ) + ( minSameNetSpacing "metal2" 0.070 ) + ( minSpacing "contact" 0.075 ) + ( minSpacing "poly" 0.075 ) + ( minWidth "nwell" 0.2 ) + ( minWidth "pwell" 0.2 ) + ( minSpacing "nwell" 0.225 ) + ( minSpacing "pwell" 0.225 ) + ( minSpacing "metal6" 0.14 ) + ( minSameNetSpacing "metal6" 0.14 ) + ( minWidth "metal6" 0.14 ) + ( minSpacing "via5" 0.16 ) + ( minWidth "via5" 0.14 ) + ( minSpacing "metal5" 0.14 ) + ( minSameNetSpacing "metal5" 0.14 ) + ( minWidth "metal5" 0.14 ) + ( minSpacing "via4" 0.16 ) + ( minWidth "via4" 0.14 ) + ( minWidth "metal4" 0.14 ) + ( minSpacing "via3" 0.085 ) + ( minWidth "via3" 0.07 ) + ( minWidth "metal3" 0.07 ) + ( minSpacing "via2" 0.085 ) + ( minWidth "via2" 0.07 ) + ( minSpacing "metal4" 0.14 ) + ( minSameNetSpacing "metal4" 0.14 ) + ( minSpacing "metal3" 0.07 ) + ( minSameNetSpacing "metal3" 0.07 ) + + ( minSpacing "metal7" 0.44 ) + ( minSameNetSpacing "metal7" 0.44 ) + ( minWidth "metal7" 0.4 ) + ( minSpacing "via6" 0.16 ) + ( minWidth "via6" 0.14 ) + ( minSpacing "metal8" 0.44 ) + ( minSameNetSpacing "metal8" 0.44 ) + ( minWidth "metal8" 0.4 ) + ( minSpacing "via7" 0.44 ) + ( minWidth "via7" 0.4 ) + ( minWidth "metal9" 0.8 ) + ( minSpacing "via8" 0.44 ) + ( minWidth "via8" 0.4 ) + ( minWidth "metal10" 0.4 ) + ( minSpacing "via9" 0.88 ) + ( minWidth "via9" 0.8 ) + ( minSpacing "metal9" 0.8 ) + ( minSameNetSpacing "metal9" 0.8 ) + ( minSpacing "metal10" 0.8 ) + ( minSameNetSpacing "metal10" 0.8 ) + + ) ;spacings + ) ;foundry +) ;constraintGroups + + +;******************************** +; DEVICES +;******************************** +devices( +tcCreateCDSDeviceClass() + +; +; no cdsVia devices +; + +; +; no cdsMos devices +; + +; +; no ruleContact devices +; + +; +; no multipartPathTemplates +; + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +; Opus Symbolic Device Class Definition +; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; +; no other device classes +; + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +; Opus Symbolic Device Declaration +; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; +; no other devices +; +) ;devices + + +;******************************** +; LE RULES +;******************************** +leRules( + + leLswLayers( + ;( layer purpose ) + ;( ----- ------- ) + ) ;leLswLayers + +) ;leRules diff --git a/technology/freepdk45/tf/README.txt b/technology/freepdk45/tf/README.txt new file mode 100644 index 00000000..5393b0b3 --- /dev/null +++ b/technology/freepdk45/tf/README.txt @@ -0,0 +1,47 @@ +These technology files are from the FreePDK45nm design kit. + +FreePDK 45nm verion 1.4 (2011-04-07) +(Subversion Repository revision 173) + +Copyright 2007 - W. Rhett Davis, Paul Franzon, Michael Bucher, + and Sunil Basavarajaiah, North Carolina State University +Copyright 2008 - W. Rhett Davis, Michael Bucher, and Sunil Basavarajaiah, + North Carolina State University (ncsu_basekit subtree) + James Stine, and Ivan Castellanos, + and Oklahoma State University (osu_soc subtree) +Copyright 2011 - W. Rhett Davis, and Harun Demircioglu, + North Carolina State University + +SVRF Technology in this kit is licensed under the the agreement found +in the file SVRF_EULA_06Feb09.txt in this directory. All other files +are licensed under the Apache License, Version 2.0 (the "License"); +you may not use these files except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +***** Welcome to the FreePDK 45nm Free, Open-Source Process Design Kit ***** + +This initiative is brought to you by the Semiconductor Research +Corporation (SRC), the National Science Foundation (NSF), Silicon +Integration Initiative (Si2), Mentor Graphics, and Synopsys. + +This version of the kit was created by Rhett Davis, Paul Franzon, +Michael Bucher, Sunil Basavarajaiah, and Harun Demircioglu +of North Carolina State University, and James Stine and Ivan Castellanos +of Oklahoma State University. + +Contributions and modifications to this kit are welcomed and encouraged. + +***** Contents ***** + +ncsu_basekit/ Base kit for custom design +osu_soc/ Standard-cell kit for synthesis, place, & route + + diff --git a/technology/freepdk45/tf/display.drf b/technology/freepdk45/tf/display.drf new file mode 100644 index 00000000..7923ae62 --- /dev/null +++ b/technology/freepdk45/tf/display.drf @@ -0,0 +1,3445 @@ +;========================================================================== +; +; $Id: display.drf 61 2007-07-24 20:05:21Z mdbucher $ +; +;-------------------------------------------------------------------------- + +drDefineDisplay( +;( DisplayName ) + ( display ) ;-- Screen -- + ( psc ) ;-- Color PS -- + ( psb ) ;-- B&W PS -- +) + + +; ------------------------------------------------------------------- +; ------ Display information for the display device 'display'. ------ +; ------------------------------------------------------------------- + +drDefineColor( +;( DisplayName ColorName Red Green Blue Blink ) +;( ----------- --------- --- ----- ---- ----- ) + ( display white 255 255 255 ) + ( display blinkWhite 255 255 255 t ) + ( display silver 217 230 255 ) + ( display cream 255 255 204 ) + ( display pink 255 191 242 ) + ( display magenta 255 0 255 ) + ( display lime 0 255 0 ) + ( display tan 255 230 191 ) + ( display cyan 0 255 255 ) + ( display cadetBlue 57 191 255 ) + ( display yellow 255 255 0 ) + ( display blinkYellow 255 255 0 t ) ; jts + ( display orange 255 128 0 ) + ( display red 255 0 0 ) + ( display purple 153 0 230 ) + ( display green 0 204 102 ) + ( display brown 191 64 38 ) + ( display blue 0 0 255 ) + ( display slate 140 140 166 ) + ( display gold 217 204 0 ) + ( display maroon 230 31 13 ) + ( display violet 94 0 230 ) + ( display forest 38 140 107 ) + ( display chocolate 128 38 38 ) + ( display navy 51 51 153 ) + ( display black 0 0 0 ) + ( display winBack 224 224 224 ) + ( display winFore 128 0 0 ) + ( display winText 51 51 51 ) + ( display winColor1 166 166 166 ) + ( display winColor2 115 115 115 ) + ( display winColor3 189 204 204 ) + ( display winColor4 204 204 204 ) + ( display winColor5 199 199 199 ) + ( display lightpink 255 196 209 ) + +;---- cmosx below ------------------------------- + ( display gray 204 204 217 ) + ( display volorange 255 164 0 ) + +) + +drDefineStipple( +;( DisplayName StippleName Bitmap ) +;( ----------- ----------- ------ ) + + ( display blank ( + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( display solid ( + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + ) ) + ( display dots ( + (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( display hLine ( + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + ) ) + ( display hLine2 ( + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + ) ) + ( display vLine ( + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + ) ) + ( display vLine2 ( + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) + ) ) + ( display cross ( + (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) + (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) + (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) + (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) + (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) + (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) + (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) + (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) + ) ) + ( display miniHatch ( + (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) + (0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0) + (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) + (0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0) + (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( display grid ( + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + ) ) + ( display slash ( + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) + (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) + (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) + (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) + (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) + (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) + (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) 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0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( display cwellBp ( + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + + ( display capID ( + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0) + (0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0) + (0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( display resID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 0 1 0 0 1 1 1 0 0 0 0 0 0 ) + ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display diodeID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) + ( 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 ) + ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + +) + +drDefineLineStyle( +;( DisplayName LineStyle Size Pattern ) +;( ----------- --------- ---- ------- ) + ( display solid 1 (1 1 1) ) + ( display dashed 1 (1 1 1 1 0 0) ) + ( display dots 1 (1 0 0) ) + ( display dashDot 1 (1 1 1 0 0 1 0 0) ) + ( display shortDash 1 (1 1 0 0) ) + ( display doubleDash 1 (1 1 1 1 0 0 1 1 0 0) ) + ( display hidden 1 (1 0 0 0) ) + ( display thickLine 3 (1 1 1) ) + ( display mLine 2 (1 1 1) ) + ) + +drDefinePacket( +;( DisplayName PacketName Stipple LineStyle Fill Outline ) +;( ----------- ---------- ------- --------- ---- ------- ) + ( display default blank solid green green ) + ( display hdrcBnd blank solid white white ) + ( display nwell wellp solid green green ) + ( display nwellNet blank solid green green ) + ( display nwellPin X solid green green ) + ( display pwell wellp solid orange orange ) + ( display pwellNet blank solid orange orange ) + ( display pwellPin X solid orange orange ) + ( display pbase checker2 solid orange orange ) + ( display pbaseNet blank solid orange orange ) + ( display pbasePin X solid orange orange ) + ( display vtg wellvtg dashed blue blue ) + ( display vtgNet blank dashed blue blue ) + ( display vth wellvth dashed blue blue ) + ( display vthNet blank dashed blue blue ) + ( display active contp solid green green ) + ( display activeNet blank solid green green ) + ( display activePin X solid green green ) + ( display thkox thickox solid yellow yellow ) + ( display thkoxLbl blank solid yellow yellow ) + ( display nimplant triangle solid green green ) + ( display pimplant triangle solid orange orange ) + ( display poly checker1 solid red red ) + ( display polyNet blank solid red red ) + ( display polyPin X solid red red ) + ( display polyLbl blank solid red red ) + ( display polyBnd blank solid red red ) + ( display sblock brick solid blue blue ) + ( display highres resID solid blue blue ) + ( display elec checker2 solid yellow yellow ) + ( display elecNet blank solid yellow yellow ) + ( display elecPin X solid yellow yellow ) + ( display elecLbl blank solid yellow yellow ) + ( display elecBnd blank solid yellow yellow ) + ( display metal1 backSlash solid blue blue ) + ( display metal1Net blank solid blue blue ) + ( display metal1Pin X solid blue blue ) + ( display metal1Lbl blank solid blue blue ) + ( display metal1Bnd blank solid blue blue ) + ( display contact X solid black lime ) + ( display contactNe blank solid brown brown ) + ( display contactPin X solid black black ) + ( display contactLbl blank solid black black ) + ( display contactBnd blank solid black black ) + ( display metal2 dots solid magenta magenta ) + ( display metal2Net blank solid magenta magenta ) + ( display metal2Pin X solid magenta magenta ) + ( display metal2Lbl blank solid magenta magenta ) + ( display metal2Bnd blank solid magenta magenta ) + ( display via1 invCross solid magenta navy ) + ( display via1Net blank solid purple black ) + ( display via1Pin X solid purple black ) + ( display via1Lbl blank solid purple black ) + ( display via1Bnd blank solid purple black ) + ( display metal3 halfslash solid cyan cyan ) + ( display metal3Net blank solid cyan cyan ) + ( display metal3Pin X solid cyan cyan ) + ( display metal3Lbl blank solid cyan cyan ) + ( display metal3Bnd blank solid cyan cyan ) + ( display via2 invCross solid cadetBlue cadetBlue ) + ( display via2Net blank solid cadetBlue cadetBlue ) + ( display via2Pin X solid cadetBlue cadetBlue ) + ( display via2Lbl blank solid cadetBlue cadetBlue ) + ( display via2Bnd blank solid cadetBlue cadetBlue ) + ( display metal4 dot4 solid cream cream ) + ( display metal4Net blank solid cream cream ) + ( display metal4Pin X solid cream cream ) + ( display metal4Lbl blank solid cream cream ) + ( display metal4Bnd blank solid cream cream ) + ( display via3 invCross solid tan tan ) + ( display via3Net blank solid tan tan ) + ( display via3Pin X solid tan tan ) + ( display via3Lbl blank solid tan tan ) + ( display via3Bnd blank solid tan tan ) + ( display metal5 metal2S solid cadetBlue cadetBlue ) + ( display metal5Net blank solid cadetBlue cadetBlue ) + ( display metal5Pin X solid cadetBlue cadetBlue ) + ( display metal5Lbl blank solid cadetBlue cadetBlue ) + ( display metal5Bnd blank solid cadetBlue cadetBlue ) + ( display via4 invCross solid blue blue ) + ( display via4Net blank solid blue blue ) + ( display via4Pin X solid blue blue ) + ( display via4Lbl blank solid blue blue ) + ( display via4Bnd blank solid blue blue ) + ( display metal6 miniHatch solid gold gold ) + ( display metal6Net blank solid gold gold ) + ( display metal6Pin X solid gold gold ) + ( display metal6Lbl blank solid gold gold ) + ( display metal6Bnd blank solid gold gold ) + ( display via5 invCross solid yellow yellow ) + ( display via5Net blank solid yellow yellow ) + ( display via5Pin X solid yellow yellow ) + ( display via5Lbl blank solid yellow yellow ) + ( display via5Bnd blank solid yellow yellow ) + ( display metal7 halfslash solid lime lime ) + ( display metal7Net blank solid lime lime ) + ( display metal7Pin X solid lime lime ) + ( display metal7Lbl blank solid lime lime ) + ( display metal7Bnd blank solid lime lime ) + ( display via6 invCross solid magenta magenta ) + ( display via6Net blank solid magenta magenta ) + ( display via6Pin X solid magenta magenta ) + ( display via6Lbl blank solid magenta magenta ) + ( display via6Bnd blank solid magenta magenta ) + ( display metal8 hLine2 solid white white ) + ( display metal8Net blank solid white white ) + ( display metal8Pin X solid white white ) + ( display metal8Lbl blank solid white white ) + ( display metal8Bnd blank solid white white ) + ( display via7 invCross solid cadetBlue cadetBlue ) + ( display via7Net blank solid cadetBlue cadetBlue ) + ( display via7Pin X solid cadetBlue cadetBlue ) + ( display via7Lbl blank solid cadetBlue cadetBlue ) + ( display via7Bnd blank solid cadetBlue cadetBlue ) + ( display metal9 vLine2 solid tan tan ) + ( display metal9Net blank solid tan tan ) + ( display metal9Pin X solid tan tan ) + ( display metal9Lbl blank solid tan tan ) + ( display metal9Bnd blank solid tan tan ) + ( display via8 invCross solid cream cream ) + ( display via8Net blank solid cream cream ) + ( display via8Pin X solid cream cream ) + ( display via8Lbl blank solid cream cream ) + ( display via8Bnd blank solid cream cream ) + ( display metal10 metal2S solid orange orange ) + ( display metal10Net blank solid orange orange ) + ( display metal10Pin X solid orange orange ) + ( display metal10Lbl blank solid orange orange ) + ( display metal10Bnd blank solid orange orange ) + ( display via9 invCross solid blue blue ) + ( display via9Net blank solid blue blue ) + ( display via9Pin X solid blue blue ) + ( display via9Lbl blank solid blue blue ) + ( display via9Bnd blank solid blue blue ) + ( display glass vLine solid slate slate ) + ( display open vCurb solid violet violet ) + ( display openNet blank solid violet violet ) + ( display openPin X solid violet violet ) + ( display openLbl blank solid violet violet ) + ( display openBnd blank solid violet violet ) + ( display pstop dagger solid maroon maroon ) + ( display pstopNet blank solid maroon maroon ) + ( display pstopPin X solid maroon maroon ) + ( display pstopLbl blank solid maroon maroon ) + ( display pstopBnd blank solid maroon maroon ) + ( display pad X doubleDash yellow yellow ) + ( display nodrc X doubleDash cyan cyan ) + ( display nolpe dot3 doubleDash tan tan ) + ( display cap_id capID doubleDash slate slate ) + ( display res_id resID doubleDash slate slate ) + ( display dio_id diodeID doubleDash slate slate ) + ( display metalcap miniHatch solid violet violet ) + ( display metalcapBnd miniHatch solid violet violet ) + ( display metalcapPin X solid violet violet ) + ( display metalcapNet blank solid violet violet ) + ( display metalcapLbl blank solid violet violet ) + ( display background solid solid black black ) + ( display grid blank solid slate slate ) + ( display grid1 blank solid white white ) + ( display axis blank solid white white ) + ( display instance blank solid red red ) + ( display instanceLbl blank solid red red ) + ( display prBoundary blank solid purple purple ) + ( display prBoundaryBnd blank solid cyan cyan ) + ( display prBoundaryLbl blank solid purple purple ) + ( display align blank solid tan tan ) + ( display hardFence blank solid red red ) + ( display softFence blank solid yellow yellow ) + ( display text blank solid white white ) + ( display text1 blank dashed white white ) + ( display text2 solid solid white white ) + ( display border blank solid tan tan ) + ( display device blank solid green green ) + ( display device2 blank dashed green green ) + ( display device1 solid solid green green ) + ( display wire solid solid cadetBlue cadetBlue ) + ( display wireLbl solid solid cadetBlue cadetBlue ) + ( display wireFlt blank dashed red red ) + ( display deviceAnt blank solid yellow yellow ) + ( display deviceLbl blank solid green green ) + ( display pinLbl blank solid red red ) + ( display pin solid solid red red ) + ( display pinAnt blank solid red red ) + ( display annotate blank solid orange orange ) + ( display annotate1 blank solid pink pink ) + ( display annotate2 blank solid lime lime ) + ( display annotate3 blank solid cyan cyan ) + ( display annotate4 blank solid yellow yellow ) + ( display annotate5 blank solid white white ) + ( display annotate6 blank solid silver silver ) + ( display annotate7 blank solid red red ) + ( display annotate8 blank solid tan tan ) + ( display annotate9 blank solid green green ) + ( display edgeLayer blank solid winColor5 winColor5 ) + ( display edgeLayerPin blank solid yellow yellow ) + ( display snap blank solid yellow yellow ) + ( display stretch blank solid yellow yellow ) + ( display y0 blank dashed magenta magenta ) + ( display y1 blank dashed brown brown ) + ( display y2 blank dashed red red ) + ( display y3 blank dashed pink pink ) + ( display y4 blank dashed orange orange ) + ( display y5 blank dashed green green ) + ( display y6 blank dashed blue blue ) + ( display y7 blank dashed purple purple ) + ( display y8 blank dashed gold gold ) + ( display y9 blank dashed silver silver ) + ( display hilite blank thickLine white white ) + ( display hilite1 blank solid magenta magenta ) + ( display hilite2 blank solid orange orange ) + ( display hilite3 blank solid cyan cyan ) + ( display hilite4 blank solid tan tan ) + ( display hilite5 blank solid lime lime ) + ( display hilite6 blank solid orange orange ) + ( display hilite7 blank solid cream cream ) + ( display hilite8 blank solid magenta magenta ) + ( display hilite9 blank solid pink pink ) + ( display implant blank solid orange orange ) + ( display drive blank solid blue blue ) + ( display hiz blank solid orange orange ) + ( display resist blank solid cyan cyan ) + ( display spike blank solid purple purple ) + ( display supply blank solid lime lime ) + ( display unknown blank solid yellow yellow ) + ( display unset blank solid forest forest ) + ( display designFlow solid solid green green ) + ( display designFlow1 solid solid red red ) + ( display designFlow2 solid solid purple purple ) + ( display designFlow3 solid solid pink pink ) + ( display designFlow4 solid solid black black ) + ( display designFlow5 solid solid silver silver ) + ( display designFlow6 solid solid tan tan ) + ( display designFlow7 solid solid cyan cyan ) + ( display designFlow8 solid solid navy navy ) + ( display designFlow9 solid solid orange orange ) + ( display changedLayerTl0 blank solid red red ) + ( display changedLayerTl1 blank solid yellow yellow ) + ( display markerWarn X solid yellow yellow ) + ( display markerErr X solid white white ) + ( display Row blank solid cyan cyan ) + ( display RowLbl blank solid cyan cyan ) + ( display Group dots solid green green ) + ( display GroupLbl blank solid green green ) + ( display Cannotoccupy X solid red red ) + ( display CannotoccupyBnd blank solid red red ) + ( display Canplace blank solid cyan cyan ) + ( display Unrouted blank dashed winColor5 winColor5 ) + ( display Unrouted1 blank dashed brown brown ) + ( display Unrouted2 blank dashed red red ) + ( display Unrouted3 blank dashed pink pink ) + ( display Unrouted4 blank dashed orange orange ) + ( display Unrouted5 blank dashed green green ) + ( display Unrouted6 blank dashed blue blue ) + ( display Unrouted7 blank dashed purple purple ) + ( display Unrouted8 blank dashed gold gold ) + ( display Unrouted9 blank dashed silver silver ) + +;---- cmosx below ------------------------------------------------------------------ + ( display NdiffResMask metal1S solid green green ) + ( display NLDD_Block dagger solid cream cream ) + ( display PLDD_Block dagger solid orange orange ) + ( display glass2 blank solid silver silver ) + ( display PdiffResMask metal1S solid brown brown ) + ( display NwellResMask metal1S solid lime lime ) + ( display PwellResMask metal1S solid orange orange ) + ( display celltag blank solid silver silver ) + ( display cellpwrtext blank solid yellow yellow ) + ( display celliotext blank solid yellow yellow ) + ( display cellnametext blank solid yellow yellow ) + ( display cellioterm blank solid yellow yellow ) + ( display cellbox blank solid yellow yellow ) + ( display PolyResMask metal1S solid red red ) + ( display M1ResMask metal1S solid blue blue ) + ( display M2ResMask metal1S solid magenta magenta ) + ( display polytext blank solid yellow yellow ) + ( display paatext blank solid yellow yellow ) + ( display naatext blank solid yellow yellow ) + ( display pwelltext blank solid yellow yellow ) + ( display nwelltext blank solid yellow yellow ) + ( display psubtext blank solid yellow yellow ) + ( display metal2text blank solid cyan cyan ) + ( display metal1text blank solid violet violet ) + ( display aaPin X solid volorange volorange ) + ( display nplus blank solid green green ) + ( display aa blank solid volorange volorange ) + ( display pplus blank solid brown brown ) + ( display aaNet blank solid volorange volorange ) + ( display contact X solid white white ) + ( display contactNet blank solid winColor5 winColor5 ) + ( display contactPin blank solid red red ) + ( display glasscut blank solid yellow yellow ) + ( display NdiffNet blank solid green green ) + ( display Ndiff dagger solid green green ) + ( display PdiffPin X solid brown brown ) + ( display NdiffPin X solid green green ) + ( display PdiffNet blank solid brown brown ) + ( display Pdiff dagger solid brown brown ) + ( display Met1TopTxt blank solid violet violet ) + ( display Met2TopTxt blank solid cyan cyan ) + ( display Met3TopTxt blank solid tan tan ) + ( display diodeMask blank solid yellow yellow ) + ( display TFDmask blank solid yellow yellow ) + ( display TABmask blank solid yellow yellow ) + ( display metal3text blank solid tan tan ) + ( display PolyNwellCap capID solid lime yellow ) + ( display PolyPwellCap capID solid brown yellow ) + ( display M1PolyCap capID solid blue yellow ) + ( display M2M1Cap capID solid magenta yellow ) + +) + + +; ---------------------------------------------------------------------------- +; ------ Display information for the display device 'psc' (Color PS). -------- +; ---------------------------------------------------------------------------- +drDefineColor( +;( DisplayName ColorName Red Green Blue Blink ) +;( ----------- --------- --- ----- ---- ----- ) + ( psc white 255 255 255 ) + ( psc silver 217 230 255 ) + ( psc cream 255 255 204 ) + ( psc pink 255 191 242 ) + ( psc magenta 255 0 255 ) + ( psc lime 0 255 0 ) + ( psc tan 255 230 191 ) + ( psc cyan 0 255 255 ) + ( psc cadetBlue 57 191 255 ) + ( psc yellow 255 255 0 ) + ( psc orange 255 128 0 ) + ( psc red 255 0 0 ) + ( psc purple 153 0 230 ) + ( psc green 0 204 102 ) + ( psc brown 191 64 38 ) + ( psc blue 0 0 255 ) + ( psc slate 140 140 166 ) + ( psc gold 217 204 0 ) + ( psc maroon 230 31 13 ) + ( psc violet 94 0 230 ) + ( psc forest 38 140 107 ) + ( psc chocolate 128 38 38 ) + ( psc navy 51 51 153 ) + ( psc black 0 0 0 ) + ( psc winBack 224 224 224 ) + ( psc winFore 128 0 0 ) + ( psc winText 51 51 51 ) + ( psc winColor1 166 166 166 ) + ( psc winColor2 115 115 115 ) + ( psc winColor3 189 204 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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( psc cwellBp ( + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( psc capID ( + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0) + (0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0) + (0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( psc resID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 0 1 0 0 1 1 1 0 0 0 0 0 0 ) + ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( psc diodeID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) + ( 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 ) + ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) +) + +drDefineLineStyle( +;( DisplayName LineStyle Size Pattern ) +;( ----------- --------- ---- ------- ) + ( psc solid 1 (1 1 1) ) + ( psc dashed 1 (1 1 1 1 0 0) ) + ( psc dots 1 (1 0 0) ) + ( psc dashDot 1 (1 1 1 0 0 1 0 0) ) + ( psc shortDash 1 (1 1 0 0) ) + ( psc doubleDash 1 (1 1 1 1 0 0 1 1 0 0) ) + ( psc hidden 1 (1 0 0 0) ) + ( psc thickLine 3 (1 1 1) ) + ( psc mLine 2 (1 1 1) ) + ) + +drDefinePacket( +;( DisplayName PacketName Stipple LineStyle Fill Outline ) +;( ----------- ---------- ------- --------- ---- ------- ) + ( psc default blank solid green green ) + ( psc hdrcBnd blank solid white white ) + ( psc nwell slash solid green green ) + ( psc nwellNet blank solid green green ) + ( psc nwellPin X solid green green ) + ( psc pwell slash solid orange orange ) + ( psc pwellNet blank solid orange orange ) + ( psc pwellPin X solid orange orange ) + ( psc pbase checker2 solid orange orange ) + ( psc pbaseNet blank solid orange orange ) + ( psc pbasePin X solid orange orange ) + ( psc active invCross solid green green ) + ( psc activeNet blank solid green green ) + ( psc activePin X solid green green ) + ( psc nimplant blank solid green green ) + ( psc pimplant blank solid orange orange ) + ( psc polycap checker2 solid lightpink lightpink ) + ( psc polycapNet blank solid lightpink lightpink ) + ( psc polycapPin X solid lightpink lightpink ) + ( psc polycapLbl blank solid lightpink lightpink ) + ( psc polycapBnd blank solid lightpink lightpink ) + ( psc poly checker1 solid red red ) + ( psc polyNet blank solid red red ) + ( psc polyPin X solid red red ) + ( psc polyLbl blank solid red red ) + ( psc polyBnd blank solid red red ) + ( psc sblock brick solid blue blue ) + ( psc highres resID solid blue blue ) + ( psc elec checker2 solid yellow yellow ) + ( psc elecNet blank solid yellow yellow ) + ( psc elecPin X solid yellow yellow ) + ( psc elecLbl blank solid yellow yellow ) + ( psc metal1 backSlash solid blue blue ) + ( psc metal1Net blank solid blue blue ) + ( psc metal1Pin X solid blue blue ) + ( psc metal1Lbl blank solid blue blue ) + ( psc metal1Bnd blank solid blue blue ) + ( psc contact solid solid black lime ) + ( psc contactNet blank solid brown brown ) + ( psc contactPin X solid black black ) + ( psc contactLbl blank solid black black ) + ( psc contactBnd blank solid black black ) + ( psc metal2 dots solid magenta magenta ) + ( psc metal2Net blank solid magenta magenta ) + ( psc metal2Pin X solid magenta magenta ) + ( psc metal2Lbl blank solid magenta magenta ) + ( psc metal2Bnd blank solid magenta magenta ) + ( psc via1 viap solid purple black ) + ( psc via1Net blank solid purple black ) + ( psc via1Pin X solid purple black ) + ( psc via1Lbl blank solid purple black ) + ( psc viaBnd blank solid purple black ) + ( psc metal3 halfslash solid cyan cyan ) + ( psc metal3Net blank solid cyan cyan ) + ( psc metal3Pin X solid cyan cyan ) + ( psc metal3Lbl blank solid cyan cyan ) + ( psc metal3Bnd blank solid cyan cyan ) + ( psc via2 brick solid black black ) + ( psc via2Net blank solid black black ) + ( psc via2Pin X solid black black ) + ( psc via2Lbl blank solid black black ) + ( psc via2Bnd blank solid black black ) + ( psc metal4 dot4 solid cream cream ) + ( psc metal4Net blank solid cream cream ) + ( psc metal4Pin X solid cream cream ) + ( psc metal4Lbl blank solid cream cream ) + ( psc metal4Bnd blank solid cream cream ) + ( psc via3 invCross solid tan tan ) + ( psc via3Net blank solid tan tan ) + ( psc via3Pin X solid tan tan ) + ( psc via3Lbl blank solid tan tan ) + ( psc via3Bnd blank solid tan tan ) + ( psc metal5 metal2S solid cadetBlue cadetBlue ) + ( psc metal5Net blank solid cadetBlue cadetBlue ) + ( psc metal5Pin X solid cadetBlue cadetBlue ) + ( psc metal5Lbl blank solid cadetBlue cadetBlue ) + ( psc metal5Bnd blank solid cadetBlue cadetBlue ) + ( psc via4 invCross solid blue blue ) + ( psc via4Net blank solid blue blue ) + ( psc via4Pin X solid blue blue ) + ( psc via4Lbl blank solid blue blue ) + ( psc via4Bnd blank solid blue blue ) + ( psc metal6 miniHatch solid gold gold ) + ( psc metal6Net blank solid gold gold ) + ( psc metal6Pin X solid gold gold ) + ( psc metal6Lbl blank solid gold gold ) + ( psc metal6Bnd blank solid gold gold ) + ( psc via5 invCross solid yellow yellow ) + ( psc via5Net blank solid yellow yellow ) + ( psc via5Pin X solid yellow yellow ) + ( psc via5Lbl blank solid yellow yellow ) + ( psc via5Bnd blank solid yellow yellow ) + ( psc metal7 dots solid maroon maroon ) + ( psc metal7Net blank solid maroon maroon ) + ( psc metal7Pin X solid maroon maroon ) + ( psc metal7Lbl blank solid maroon maroon ) + ( psc metal7Bnd blank solid maroon maroon ) + ( psc via6 invCross solid magenta magenta ) + ( psc viaNet6 blank solid magenta magenta ) + ( psc viaPin6 X solid magenta magenta ) + ( psc viaLbl6 blank solid magenta magenta ) + ( psc viaBnd6 blank solid magenta magenta ) + ( psc metal8 halfslash solid cyan cyan ) + ( psc metal8Net blank solid cyan cyan ) + ( psc metal8Pin X solid cyan cyan ) + ( psc metal8Lbl blank solid cyan cyan ) + ( psc metal8Bnd blank solid cyan cyan ) + ( psc via7 invCross solid cadetBlue cadetBlue ) + ( psc via7Net blank solid cadetBlue cadetBlue ) + ( psc via7Pin X solid cadetBlue cadetBlue ) + ( psc via7Lbl blank solid cadetBlue cadetBlue ) + ( psc via7Bnd blank solid cadetBlue cadetBlue ) + ( psc metal9 dot4 solid cream cream ) + ( psc metal9Net blank solid cream cream ) + ( psc metal9Pin X solid cream cream ) + ( psc metal9Lbl blank solid cream cream ) + ( psc metal9Bnd blank solid cream cream ) + ( psc via8 invCross solid tan tan ) + ( psc via8Net blank solid tan tan ) + ( psc via8Pin X solid tan tan ) + ( psc via8Lbl blank solid tan tan ) + ( psc via8Bnd blank solid tan tan ) + ( psc metal10 metal2S solid cadetBlue cadetBlue ) + ( psc metal10Net blank solid cadetBlue cadetBlue ) + ( psc metal10Pin X solid cadetBlue cadetBlue ) + ( psc metal10Lbl blank solid cadetBlue cadetBlue ) + ( psc metal10Bnd blank solid cadetBlue cadetBlue ) + ( psc via9 invCross solid blue blue ) + ( psc via9Net blank solid blue blue ) + ( psc via9Pin X solid blue blue ) + ( psc via9Lbl blank solid blue blue ) + ( psc via9Bnd blank solid blue blue ) + ( psc metal11 miniHatch solid gold gold ) + ( psc metal11Net blank solid gold gold ) + ( psc metal11Pin X solid gold gold ) + ( psc metal11Lbl blank solid gold gold ) + ( psc metal11Bnd blank solid gold gold ) + ( psc glass vLine solid slate slate ) + ( psc open vCurb solid violet violet ) + ( psc openNet blank solid violet violet ) + ( psc openPin X solid violet violet ) + ( psc openLbl blank solid violet violet ) + ( psc openBnd blank solid violet violet ) + ( psc pstop dagger solid maroon maroon ) + ( psc pstopNet blank solid maroon maroon ) + ( psc pstopPin X solid maroon maroon ) + ( psc pstopLbl blank solid maroon maroon ) + ( psc pstopBnd blank solid maroon maroon ) + ( psc pad X doubleDash yellow yellow ) + ( psc nodrc X doubleDash cyan cyan ) + ( psc nolpe dot3 doubleDash tan tan ) + ( psc cap_id capID doubleDash slate slate ) + ( psc res_id resID doubleDash slate slate ) + ( psc dio_id diodeID doubleDash slate slate ) + ( psc metalcap miniHatch solid violet violet ) + ( psc metalcapBnd miniHatch solid violet violet ) + ( psc metalcapPin X solid violet violet ) + ( psc metalcapNet blank solid violet violet ) + ( psc metalcapLbl blank solid violet violet ) + ( psc background solid solid black black ) + ( psc grid blank solid slate slate ) + ( psc grid1 blank solid white white ) + ( psc axis blank solid white white ) + ( psc instance blank solid red red ) + ( psc instanceLbl blank solid gold gold ) + ( psc prBoundary blank solid purple purple ) + ( psc prBoundaryBnd blank solid cyan cyan ) + ( psc prBoundaryLbl blank solid purple purple ) + ( psc align blank solid tan tan ) + ( psc hardFence blank solid red red ) + ( psc softFence blank solid yellow yellow ) + ( psc text blank solid white white ) + ( psc text1 blank dashed white white ) + ( psc text2 solid solid white white ) + ( psc border blank solid tan tan ) + ( psc device blank solid green green ) + ( psc device2 blank dashed green green ) + ( psc device1 solid solid green green ) + ( psc wire solid solid cadetBlue cadetBlue ) + ( psc wireLbl solid solid cadetBlue cadetBlue ) + ( psc wireFlt blank dashed red red ) + ( psc deviceAnt blank solid yellow yellow ) + ( psc deviceLbl blank solid green green ) + ( psc pinLbl blank solid red red ) + ( psc pin solid solid red red ) + ( psc pinAnt blank solid red red ) + ( psc annotate blank solid orange orange ) + ( psc annotate1 blank solid pink pink ) + ( psc annotate2 blank solid lime lime ) + ( psc annotate3 blank solid cyan cyan ) + ( psc annotate4 blank solid yellow yellow ) + ( psc annotate5 blank solid white white ) + ( psc annotate6 blank solid silver silver ) + ( psc annotate7 blank solid red red ) + ( psc annotate8 blank solid tan tan ) + ( psc annotate9 blank solid green green ) + ( psc edgeLayer blank solid winColor5 winColor5 ) + ( psc edgeLayerPin blank solid yellow yellow ) + ( psc snap blank solid yellow yellow ) + ( psc stretch blank solid yellow yellow ) + ( psc y0 blank dashed winColor5 winColor5 ) + ( psc y1 blank dashed brown brown ) + ( psc y2 blank dashed red red ) + ( psc y3 blank dashed pink pink ) + ( psc y4 blank dashed orange orange ) + ( psc y5 blank dashed green green ) + ( psc y6 blank dashed blue blue ) + ( psc y7 blank dashed purple purple ) + ( psc y8 blank dashed gold gold ) + ( psc y9 blank dashed silver silver ) + ( psc hilite blank solid white white ) + ( psc hilite1 blank solid yellow yellow ) + ( psc hilite2 blank solid tan tan ) + ( psc hilite3 blank solid cyan cyan ) + ( psc hilite4 blank solid orange orange ) + ( psc hilite5 blank solid lime lime ) + ( psc hilite6 blank solid orange orange ) + ( psc hilite7 blank solid cream cream ) + ( psc hilite8 blank solid magenta magenta ) + ( psc hilite9 blank solid pink pink ) + ( psc select blank solid orange orange ) + ( psc drive blank solid blue blue ) + ( psc hiz blank solid orange orange ) + ( psc resist blank solid cyan cyan ) + ( psc spike blank solid purple purple ) + ( psc supply blank solid lime lime ) + ( psc unknown blank solid yellow yellow ) + ( psc unset blank solid forest forest ) + ( psc designFlow solid solid green green ) + ( psc designFlow1 solid solid red red ) + ( psc designFlow2 solid solid purple purple ) + ( psc designFlow3 solid solid pink pink ) + ( psc designFlow4 solid solid black black ) + ( psc designFlow5 solid solid silver silver ) + ( psc designFlow6 solid solid tan tan ) + ( psc designFlow7 solid solid cyan cyan ) + ( psc designFlow8 solid solid navy navy ) + ( psc designFlow9 solid solid orange orange ) + ( psc changedLayerTl0 blank solid red red ) + ( psc changedLayerTl1 blank solid yellow yellow ) + ( psc markerWarn X solid yellow yellow ) + ( psc markerErr X solid white white ) + ( psc Row blank solid cyan cyan ) + ( psc RowLbl blank solid cyan cyan ) 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(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( psb dot2 ( + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0) + (0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0) + (0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( psb dot3 ( + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( psb checker ( + (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) + (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) + (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) + (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) + (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) + (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) + (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) + (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) + (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) + (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) + (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) + (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) + (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) + (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) + (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) + (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) + ) ) + ( psb checker2 ( + (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) + (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) + (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) + (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) + (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) + (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) + (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) + (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) + (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) + (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) + (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) + (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) + (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) + (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) + (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) + (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) + ) ) + ( psb sgrid ( + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) + (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) + ) ) + ( psb metal1S ( + (1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1) + ) ) + ( psb metal2S ( + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0) + (0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0) + (0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( psb gnd2S ( + (1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1) + (1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0) + (1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0) + (0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0) + (0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0) + (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) + (0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0) + (0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0) + (1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1) + (1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0) + (1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0) + (0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0) + (0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0) + (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) + (0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0) + (0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0) + ) ) + ( psb vcc2S ( + (0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0) + (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) + (0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0) + (0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0) + (1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0) + (0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0) + (0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0) + (0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0) + (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) + (0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0) + (0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0) + (1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1) + (1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0) + (0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0) + (0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0) + ) ) + ( psb vcc1S ( + (1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0) + (0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0) + (0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0) + (0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0) + (1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1) + (1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0) + (0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0) + (0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1) + (1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0) + (0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0) + (0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0) + (0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0) + (1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1) + (1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0) + (0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0) + (0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1) + ) ) + ( psb capID ( + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0) + (0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0) + (0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + ) ) + ( psb resID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 0 1 0 0 1 1 1 0 0 0 0 0 0 ) + ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( psb diodeID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) + ( 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 ) + ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) +) + +drDefineLineStyle( +;( DisplayName LineStyle Size Pattern ) +;( ----------- --------- ---- ------- ) + ( psb solid 1 (1 1 1) ) + ( psb dashed 1 (1 1 1 1 0 0 0 0) ) + ( psb dots 1 (1 0 0 0 0) ) + ( psb dashDot 1 (1 1 1 1 0 0 0 0 1 0 0 0 0) ) + ( psb shortDash 1 (1 1 0 0) ) + ( psb doubleDash 1 (1 1 1 1 0 0 0 0 1 1 0 0) ) + ( psb hidden 1 (1 0 0 0 0 0 0 0 0) ) + ( psb thickLine 3 (1 1 1) ) + ) + +drDefinePacket( +;( DisplayName PacketName Stipple LineStyle Fill Outline ) +;( ----------- ---------- ------- --------- ---- ------- ) + ( psb default blank solid 1 1 ) + ( psb nwell blank solid 1 1 ) + ( psb nwellNet blank solid 1 1 ) + ( psb nwellPin X solid 1 1 ) + ( psb pwell dot1 solid 1 1 ) + ( psb pwellNet blank solid 1 1 ) + ( psb pwellPin X solid 1 1 ) + ( psb pbase blank solid 1 1 ) + ( psb pbaseNet blank solid 1 1 ) + ( psb pbasePin X solid 1 1 ) + ( psb active dot3 solid 1 1 ) + ( psb activeNet blank solid 1 1 ) + ( psb activePin X solid 1 1 ) + ( psb nimplant blank solid 1 1 ) + ( psb pimplant blank doubleDash 1 1 ) + ( psb polycap checker2 solid 1 1 ) + ( psb polycapNet blank solid 1 1 ) + ( psb polycapPin X solid 1 1 ) + ( psb polycapLbl blank solid 1 1 ) + ( psb polycapBnd blank solid 1 1 ) + ( psb poly checker solid 1 1 ) + ( psb polyNet blank solid 1 1 ) + ( psb polyPin X solid 1 1 ) + ( psb polyLbl blank solid 1 1 ) + ( psb polyBnd blank solid 1 1 ) + ( psb sblock vCurb solid 1 1 ) + ( psb highres vCurb solid 1 1 ) + ( psb elec dagger solid 1 1 ) + ( psb elecNet blank solid 1 1 ) + ( psb elecPin X solid 1 1 ) + ( psb elecLbl blank solid 1 1 ) + ( psb metal1 metal1S thickLine 1 1 ) + ( psb metal1Net blank solid 1 1 ) + ( psb metal1Pin X solid 1 1 ) + ( psb metal1Lbl blank solid 1 1 ) + ( psb metal1Bnd blank solid 1 1 ) + ( psb contact solid solid 1 1 ) + ( psb contactNet blank solid 1 1 ) + ( psb contactPin X solid 1 1 ) + ( psb contactLbl blank solid 1 1 ) + ( psb contactBnd blank solid 1 1 ) + ( psb metal2 metal2S thickLine 1 1 ) + ( psb metal2Net blank solid 1 1 ) + ( psb metal2Pin X solid 1 1 ) + ( psb metal2Lbl blank solid 1 1 ) + ( psb metal2Bnd blank solid 1 1 ) + ( psb metal3 halfslash thickLine 1 1 ) + ( psb metal3Net blank solid 1 1 ) + ( psb metal3Pin X solid 1 1 ) + ( psb metal3Lbl blank solid 1 1 ) + ( psb metal3Bnd blank solid 1 1 ) + ( psb via2 dot1 thickLine 1 1 ) + ( psb via2Net blank solid 1 1 ) + ( psb via2Pin X solid 1 1 ) + ( psb via2Lbl blank solid 1 1 ) + ( psb via2Bnd blank solid 1 1 ) + ( psb metal4 hCurb thickLine 1 1 ) + ( psb metal4Net blank solid 1 1 ) + ( psb metal4Pin X solid 1 1 ) + ( psb metal4Lbl blank solid 1 1 ) + ( psb metal4Bnd blank solid 1 1 ) + ( psb via3 triangle thickLine 1 1 ) + ( psb via3Net blank solid 1 1 ) + ( psb via3Pin X solid 1 1 ) + ( psb via3Lbl blank solid 1 1 ) + ( psb via3Bnd blank solid 1 1 ) + ( psb metal5 hLine2 thickLine 1 1 ) + ( psb metal5Net blank solid 1 1 ) + ( psb metal5Pin X solid 1 1 ) + ( psb metal5Lbl blank solid 1 1 ) + ( psb metal5Bnd blank solid 1 1 ) + ( psb via4 dagger thickLine 1 1 ) + ( psb via4Net blank solid 1 1 ) + ( psb via4Pin X solid 1 1 ) + ( psb via4Lbl blank solid 1 1 ) + ( psb via4Bnd blank solid 1 1 ) + ( psb metal6 miniHatch solid 1 1 ) + ( psb metal6Net blank solid 1 1 ) + ( psb metal6Pin X solid 1 1 ) + ( psb metal6Lbl blank solid 1 1 ) + ( psb metal6Bnd blank solid 1 1 ) + ( psb via5 dot2 solid 1 1 ) + ( psb via5Net blank solid 1 1 ) + ( psb via5Pin X solid 1 1 ) + ( psb via5Lbl blank solid 1 1 ) + ( psb via5Bnd blank solid 1 1 ) + ( psb metal7 dots solid 1 1 ) + ( psb metal7Net blank solid 1 1 ) + ( psb metal7Pin X solid 1 1 ) + ( psb metal7Lbl blank solid 1 1 ) + ( psb metal7Bnd blank solid 1 1 ) + ( psb via6 dot2 solid 1 1 ) + ( psb viaNet6 blank solid 1 1 ) + ( psb viaPin6 X solid 1 1 ) + ( psb viaLbl6 blank solid 1 1 ) + ( psb viaBnd6 blank solid 1 1 ) + ( psb metal8 halfslash solid 1 1 ) + ( psb metal8Net blank solid 1 1 ) + ( psb metal8Pin X solid 1 1 ) + ( psb metal8Lbl blank solid 1 1 ) + ( psb metal8Bnd blank solid 1 1 ) + ( psb via7 dot2 solid 1 1 ) + ( psb via7Net blank solid 1 1 ) + ( psb via7Pin X solid 1 1 ) + ( psb via7Lbl blank solid 1 1 ) + ( psb via7Bnd blank solid 1 1 ) + ( psb metal9 dot2 solid 1 1 ) + ( psb metal9Net blank solid 1 1 ) + ( psb metal9Pin X solid 1 1 ) + ( psb metal9Lbl blank solid 1 1 ) + ( psb metal9Bnd blank solid 1 1 ) + ( psb via8 dot2 solid 1 1 ) + ( psb via8Net blank solid 1 1 ) + ( psb via8Pin X solid 1 1 ) + ( psb via8Lbl blank solid 1 1 ) + ( psb via8Bnd blank solid 1 1 ) + ( psb metal10 metal2S solid 1 1 ) + ( psb metal10Net blank solid 1 1 ) + ( psb metal10Pin X solid 1 1 ) + ( psb metal10Lbl blank solid 1 1 ) + ( psb metal10Bnd blank solid 1 1 ) + ( psb via9 dot2 solid 1 1 ) + ( psb via9Net blank solid 1 1 ) + ( psb via9Pin X solid 1 1 ) + ( psb via9Lbl blank solid 1 1 ) + ( psb via9Bnd blank solid 1 1 ) + ( psb metal11 miniHatch solid 1 1 ) + ( psb metal11Net blank solid 1 1 ) + ( psb metal11Pin X solid 1 1 ) + ( psb metal11Lbl blank solid 1 1 ) + ( psb metal11Bnd blank solid 1 1 ) + + + + + ( psb glass blank solid 1 1 ) + ( psb open vCurb solid 1 1 ) + ( psb openNet blank solid 1 1 ) + ( psb openPin blank solid 1 1 ) + ( psb openLbl blank solid 1 1 ) + ( psb openBnd blank solid 1 1 ) + ( psb pstop dagger solid 1 1 ) + ( psb pstopNet blank solid 1 1 ) + ( psb pstopPin X solid 1 1 ) + ( psb pstopLbl blank solid 1 1 ) + ( psb pstopBnd blank solid 1 1 ) + ( psb pad X doubleDash 1 1 ) + ( psb nodrc X doubleDash 1 1 ) + ( psb cap_id capID doubleDash 1 1 ) + ( psb res_id resID doubleDash 1 1 ) + ( psb dio_id diodeID doubleDash 1 1 ) + ( psb metalcap miniHatch solid 1 1 ) + ( psb metalcapBnd miniHatch solid 1 1 ) + ( psb metalcapPin X solid 1 1 ) + ( psb metalcapNet blank solid 1 1 ) + ( psb metalcapLbl blank solid 1 1 ) + ( psb background solid solid 1 1 ) + ( psb grid blank solid 1 1 ) + ( psb grid1 blank solid 1 1 ) + ( psb axis blank solid 1 1 ) + ( psb instance blank solid 1 1 ) + ( psb instanceLbl blank solid 1 1 ) + ( psb prBoundary blank solid 1 1 ) + ( psb prBoundaryBnd blank solid 1 1 ) + ( psb align blank solid 1 1 ) + ( psb text blank solid 1 1 ) + ( psb text1 blank solid 1 1 ) + ( psb text2 solid solid 1 1 ) + ( psb border solid solid 1 1 ) + ( psb device blank solid 1 1 ) + ( psb device1 blank solid 1 1 ) + ( psb wire solid solid 1 1 ) + ( psb wireLbl solid solid 1 1 ) + ( psb wireFlt blank solid 1 1 ) + ( psb deviceAnt blank solid 1 1 ) + ( psb deviceLbl blank solid 1 1 ) + ( psb pinLbl blank solid 1 1 ) + ( psb pin solid solid 1 1 ) + ( psb pinAnt blank solid 1 1 ) + ( psb annotate blank solid 1 1 ) + ( psb annotate1 blank solid 1 1 ) + ( psb annotate2 blank solid 1 1 ) + ( psb annotate3 blank solid 1 1 ) + ( psb annotate4 blank solid 1 1 ) + ( psb annotate5 blank solid 1 1 ) + ( psb annotate6 blank solid 1 1 ) + ( psb annotate7 blank solid 1 1 ) + ( psb annotate8 blank solid 1 1 ) + ( psb annotate9 blank solid 1 1 ) + ( psb edgeLayer blank solid 1 1 ) + ( psb edgeLayerPin blank solid 1 1 ) + ( psb snap blank solid 1 1 ) + ( psb stretch blank solid 1 1 ) + ( psb y0 blank solid 1 1 ) + ( psb y1 blank dashed 1 1 ) + ( psb y2 blank dots 1 1 ) + ( psb y3 blank dashDot 1 1 ) + ( psb y4 blank shortDash 1 1 ) + ( psb y5 blank doubleDash 1 1 ) + ( psb y6 blank hidden 1 1 ) + ( psb y7 blank thickLine 1 1 ) + ( psb y8 blank solid 1 1 ) + ( psb y9 hLine dashed 1 1 ) + ( psb hilite blank solid 1 1 ) + ( psb hilite1 blank solid 1 1 ) + ( psb hilite2 blank solid 1 1 ) + ( psb hilite3 blank solid 1 1 ) + ( psb hilite4 blank solid 1 1 ) + ( psb hilite5 blank solid 1 1 ) + ( psb hilite6 blank solid 1 1 ) + ( psb hilite7 blank solid 1 1 ) + ( psb hilite8 blank solid 1 1 ) + ( psb hilite9 blank solid 1 1 ) + ( psb select blank solid 1 1 ) + ( psb drive blank solid 1 1 ) + ( psb hiz blank solid 1 1 ) + ( psb resist blank solid 1 1 ) + ( psb spike blank solid 1 1 ) + ( psb supply blank solid 1 1 ) + ( psb designFlow solid solid 1 1 ) + ( psb designFlow1 blank solid 1 1 ) + ( psb designFlow2 blank solid 1 1 ) + ( psb designFlow3 blank solid 1 1 ) + ( psb designFlow4 blank solid 1 1 ) + ( psb designFlow5 blank solid 1 1 ) + ( psb designFlow6 blank solid 1 1 ) + ( psb designFlow7 blank solid 1 1 ) + ( psb designFlow8 blank solid 1 1 ) + ( psb designFlow9 blank solid 1 1 ) + ( psb changedLayerTl0 blank solid 1 1 ) + ( psb changedLayerTl1 blank solid 1 1 ) + ( psb markerWarn X solid 1 1 ) + ( psb markerErr X solid 1 1 ) +) + +; vim:ts=4:columns=132: diff --git a/technology/freepdk45/tf/glade_freepdk45.py b/technology/freepdk45/tf/glade_freepdk45.py new file mode 100644 index 00000000..09ad83ea --- /dev/null +++ b/technology/freepdk45/tf/glade_freepdk45.py @@ -0,0 +1,7 @@ +import os +CWD = os.environ.get("OPENRAM_TECH") + "/freepdk45/tf" +ui().importCds("default", CWD+"/display.drf", CWD+"/FreePDK45.tf", 1000, 1, CWD+"/layers.map") + + + + diff --git a/technology/freepdk45/tf/layers.map b/technology/freepdk45/tf/layers.map new file mode 100644 index 00000000..8c0c18d2 --- /dev/null +++ b/technology/freepdk45/tf/layers.map @@ -0,0 +1,30 @@ +active drawing 1 0 +pwell drawing 2 0 +nwell drawing 3 0 +nimplant drawing 4 0 +pimplant drawing 5 0 +vtg drawing 6 0 +vth drawing 7 0 +thkox drawing 8 0 +poly drawing 9 0 +contact drawing 10 0 +metal1 drawing 11 0 +via1 drawing 12 0 +metal2 drawing 13 0 +via2 drawing 14 0 +metal3 drawing 15 0 +via3 drawing 16 0 +metal4 drawing 17 0 +via4 drawing 18 0 +metal5 drawing 19 0 +via5 drawing 20 0 +metal6 drawing 21 0 +via6 drawing 22 0 +metal7 drawing 23 0 +via7 drawing 24 0 +metal8 drawing 25 0 +via8 drawing 26 0 +metal9 drawing 27 0 +via9 drawing 28 0 +metal10 drawing 29 0 +text drawing 239 0 diff --git a/technology/scn3me_subm/models/ff/nmos.sp b/technology/scn3me_subm/models/ff/nmos.sp index 278dfc57..9711c533 100644 --- a/technology/scn3me_subm/models/ff/nmos.sp +++ b/technology/scn3me_subm/models/ff/nmos.sp @@ -5,6 +5,6 @@ * models from MOSIS or SCN3ME ********************************************* -.MODEL n NMOS (LEVEL=49 VTHO=0.669845 KP=113.7771E-6 +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 + NSUB=6E16 U0=461 K1=0.5705 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/models/ff/pmos.sp b/technology/scn3me_subm/models/ff/pmos.sp index 86ad3cf1..e08967e4 100644 --- a/technology/scn3me_subm/models/ff/pmos.sp +++ b/technology/scn3me_subm/models/ff/pmos.sp @@ -5,5 +5,5 @@ * models from MOSIS or SCN3ME ********************************************* -.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 KP=366.0244-6 +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 + NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/models/nom/nmos.sp b/technology/scn3me_subm/models/nom/nmos.sp index 150788b4..59f88cfd 100644 --- a/technology/scn3me_subm/models/nom/nmos.sp +++ b/technology/scn3me_subm/models/nom/nmos.sp @@ -5,5 +5,5 @@ * models from MOSIS or SCN3ME ********************************************* -.MODEL n NMOS (LEVEL=49 VTHO=0.669845 KP=113.7771E-6 +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 + NSUB=6E16 U0=458 K1=0.5705 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/models/nom/pmos.sp b/technology/scn3me_subm/models/nom/pmos.sp index 4cf58290..69f3aacd 100644 --- a/technology/scn3me_subm/models/nom/pmos.sp +++ b/technology/scn3me_subm/models/nom/pmos.sp @@ -5,5 +5,5 @@ * models from MOSIS or SCN3ME ********************************************* -.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 KP=366.0244-6 +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 + NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/models/ss/nmos.sp b/technology/scn3me_subm/models/ss/nmos.sp index 1728b331..4e8a531f 100644 --- a/technology/scn3me_subm/models/ss/nmos.sp +++ b/technology/scn3me_subm/models/ss/nmos.sp @@ -5,6 +5,6 @@ * models from MOSIS or SCN3ME ********************************************* -.MODEL n NMOS (LEVEL=49 VTHO=0.669845 KP=113.7771E-6 +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 + NSUB=6E16 U0=460 K1=0.5705 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/models/ss/pmos.sp b/technology/scn3me_subm/models/ss/pmos.sp index 86ad3cf1..e08967e4 100644 --- a/technology/scn3me_subm/models/ss/pmos.sp +++ b/technology/scn3me_subm/models/ss/pmos.sp @@ -5,5 +5,5 @@ * models from MOSIS or SCN3ME ********************************************* -.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 KP=366.0244-6 +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 + NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/sp_lib/ms_flop.sp b/technology/scn3me_subm/sp_lib/ms_flop.sp index 4cdf309f..abf664e7 100644 --- a/technology/scn3me_subm/sp_lib/ms_flop.sp +++ b/technology/scn3me_subm/sp_lib/ms_flop.sp @@ -1,10 +1,5 @@ *master-slave flip-flop with both output and inverted ouput -.subckt ms_flop din dout dout_bar clk vdd gnd -xmaster din mout mout_bar clk clk_bar vdd gnd dlatch -xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch -.ends flop - .subckt dlatch din dout dout_bar clk clk_bar vdd gnd *clk inverter mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1 @@ -27,3 +22,8 @@ mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1 mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1 .ends dlatch +.subckt ms_flop din dout dout_bar clk vdd gnd +xmaster din mout mout_bar clk clk_bar vdd gnd dlatch +xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch +.ends flop + diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index fbb4cb7b..faafb7db 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -246,7 +246,21 @@ spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] +# analytical power parameters, many values are temporary +spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW +spice["inv_leakage"] = 1 # Leakage power of inverter in nW +spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW +spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW +spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW +spice["msflop_leakage"] = 1 # Leakage power of flop in nW +spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF +spice["default_event_rate"] = 100 # Default event activity of every gate. MHz +spice["flop_transisition_prob"] = .5 # Transition probability of inverter. +spice["inv_transisition_prob"] = .5 # Transition probability of inverter. +spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand. +spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand. +spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor. ################################################### ##END Spice Simulation Parameters ################################################### diff --git a/technology/scn3me_subm/tf/LICENSE b/technology/scn3me_subm/tf/LICENSE new file mode 100644 index 00000000..8d22c4be --- /dev/null +++ b/technology/scn3me_subm/tf/LICENSE @@ -0,0 +1,4 @@ +The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004, +2006. Users are free to use or modify the NCSU CDK as appropriate as long +as this notice appears in the modified package. The NCSU CDK is +provided with NO WARRANTY. diff --git a/technology/scn3me_subm/tf/README b/technology/scn3me_subm/tf/README new file mode 100644 index 00000000..400cfe98 --- /dev/null +++ b/technology/scn3me_subm/tf/README @@ -0,0 +1,19 @@ +;; NCSU CDK v. 1.6.0.beta +;; Last Modified: 2007-07-12 + +The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004, +2006, 2007. Users are free to use or modify the NCSU CDK as appropriate as long +as this notice appears in the modified package. The NCSU CDK is +provided with NO WARRANTY. + +As of version 1.5.1, all documentation for the NCSU CDK is provided +by the NCSU EDA Wiki which can be found at: + + http://www.eda.ncsu.edu/ + +This beta release of the kit is to be used in migrating to Cadence Virtuoso 6.1 +for OpenAccess. Details of the conversion of the CDK from the CDB version can +be found in the file cdb2oa/OA_Conversion.txt. + +This kit is not yet fully supported. Please post problems and solutions at +http://www.chiptalk.org -> Forums -> NCSU CDK -> NCSU CDK 1.6.0.beta for Virtuoso 6.1 diff --git a/technology/scn3me_subm/tf/display.drf b/technology/scn3me_subm/tf/display.drf new file mode 100644 index 00000000..e9a22348 --- /dev/null +++ b/technology/scn3me_subm/tf/display.drf @@ -0,0 +1,714 @@ +drDefineDisplay( +;( DisplayName ) + ( display ) +) +drDefineColor( +;( DisplayName ColorsName Red Green Blue ) + ( display white 255 255 255 ) + ( display yellow 255 255 0 ) + ( display silver 217 230 255 ) + ( display cream 255 255 204 ) + ( display pink 255 191 242 ) + ( display magenta 255 0 255 ) + ( display lime 0 255 0 ) + ( display tan 255 230 191 ) + ( display cyan 0 255 255 ) + ( display cadetBlue 57 191 255 ) + ( display orange 255 128 0 ) + ( display red 255 51 51 ) + ( display purple 153 0 230 ) + ( display green 0 204 102 ) + ( display brown 191 64 38 ) + ( display blue 51 77 255 ) + ( display slate 140 140 166 ) + ( display gold 217 204 0 ) + ( display maroon 230 31 13 ) + ( display violet 94 0 230 ) + ( display forest 38 140 107 ) + ( display chocolate 128 38 38 ) + ( display navy 51 51 153 ) + ( display black 0 0 0 ) + ( display gray 204 204 217 ) + ( display winColor1 166 166 166 ) + ( display winColor2 115 115 115 ) + ( display winColor3 189 204 204 ) + ( display winColor4 204 204 204 ) + ( display winColor5 199 199 199 ) + ( display blinkRed 255 0 0 t ) + ( display blinkYellow 255 255 0 t ) + ( display blinkWhite 255 255 255 t ) + ( display winBack 224 224 224 ) + ( display winFore 128 0 0 ) + ( display winText 51 51 51 ) +) +drDefineStipple( +;( DisplayName StippleName Bitmap ) + ( display dots ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display dots1 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display hLine ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) ) + ( display vLine ( ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) ) + ( display cross ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) ) ) + ( display grid ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) ) + ( display slash ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) ) + ( display backSlash ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) ) + ( display hZigZag ( ( 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 ) + ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 ) + ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 ) + ( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ) + ( 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 ) + ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) + ( 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ) + ( 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 ) + ( 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 ) + ( 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 ) + ( 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ) ) ) + ( display vZigZag ( ( 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 ) + ( 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) + ( 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) + ( 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 ) + ( 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 ) + ( 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 ) + ( 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 ) + ( 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 ) + ( 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 ) + ( 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) + ( 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) + ( 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 ) + ( 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 ) + ( 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 ) + ( 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 ) + ( 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 ) ) ) + ( display hCurb ( ( 0 0 0 0 0 0 0 0 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dots1 lineStyle0 orange orange outlineStipple) + ( display deviceAnt stipple0 solid yellow yellow solid ) + ( display winBottomShadow solid solid winColor1 winColor1 solid ) + ( display PselectNet dots4 solid brown brown outlineStipple) + ( display comment stipple0 lineStyle0 winBack winBack solid ) + ( display Poly1 dots lineStyle0 red red outlineStipple) + ( display Unrouted stipple0 lineStyle1 winColor5 winColor5 solid ) + ( display stretch stipple0 solid yellow yellow solid ) + ( display XP blank lineStyle0 winBack gold outline ) + ( display annotate1 stipple0 solid pink pink solid ) + ( display Group stipple2 solid green green outlineStipple) + ( display deviceLbl stipple0 solid green green solid ) + ( display annotate6 stipple0 solid silver silver solid ) + ( display GlassNet blank solid yellow yellow outline ) + ( display Canplace blank solid cyan cyan outline ) + ( display annotate7 stipple0 solid red red solid ) + ( display Via2 solid solid navy navy solid ) + ( display Metal2Pin stipple0 lineStyle0 magenta magenta solid ) + ( display annotate4 stipple0 solid yellow yellow solid ) + ( display device1 stipple1 lineStyle0 green green outlineStipple) + ( display "90" blank solid white white outline ) + ( display markerWarn x solid yellow yellow outlineStipple) + ( display text2 stipple1 lineStyle0 white white outlineStipple) + ( display CapacitorNet dots4 lineStyle0 tan tan outlineStipple) + ( display designFlow stipple1 lineStyle0 green green outlineStipple) + ( display hilite1 stipple0 solid silver silver solid ) + ( display device blank solid green green outline ) + ( display prBoundary stipple0 solid purple purple solid ) + ( display annotate5 stipple0 solid white white solid ) + ( display text1 stipple0 dashed white white solid ) + ( display Via solid solid magenta magenta solid ) + ( display Capacitor stipple7 lineStyle0 tan tan outlineStipple) + ( display markerErr x solid white white outlineStipple) + ( display unknown stipple0 solid yellow yellow solid ) + ( display annotate stipple0 solid orange orange solid ) + ( display P1ConNet x solid red red outlineStipple) + ( display hilite3 stipple0 solid cyan cyan solid ) + ( display winActiveBanner solid solid winColor3 winColor3 solid ) + ( display pinLbl stipple0 solid red red solid ) + ( display device2 stipple0 lineStyle1 green green solid ) + ( display grid stipple0 solid slate slate solid ) + ( display winBackground solid solid winBack winBack solid ) + ( display Metal1Net dots4 lineStyle0 blue blue outlineStipple) + ( display hilite2 stipple0 solid tan tan solid ) + ( display annotate8 stipple0 solid tan tan solid ) + ( display hilite5 stipple0 solid lime lime solid ) + ( display annotate9 stipple0 solid green green solid ) + ( display Metal2Net dots4 lineStyle0 magenta magenta outlineStipple) + ( display Metal3Pin stipple0 solid navy navy solid ) + ( display hilite4 stipple0 solid gray gray solid ) + ( display y0 stipple0 solid gray gray solid ) + ( display supply stipple0 solid lime lime solid ) + ( display ActiveNet dots4 lineStyle0 yellow yellow outlineStipple) + ( display hilite7 stipple0 solid cream cream solid ) + ( display y1 stipple0 solid brown brown solid ) + ( display defaultPacket x solid chocolate winColor2 outlineStipple) + ( display Via2Net cross solid navy navy outlineStipple) + ( display NselectNet dots4 solid green green outlineStipple) + ( display Unrouted8 stipple0 lineStyle1 gold gold solid ) + ( display hilite6 stipple0 solid orange orange solid ) + ( display y2 stipple0 solid red red solid ) + ( display winBorder solid solid winColor2 winColor2 solid ) + ( display Nwell dats5 thickLine slate slate outlineStipple) + ( display Unrouted9 stipple0 lineStyle1 silver silver solid ) + ( display hilite9 stipple0 solid pink pink solid ) + ( display SiBlock blank dashed tan tan outline ) + ( display y3 stipple0 solid orange orange solid ) + ( display prBoundaryBnd stipple0 solid cyan cyan solid ) + ( display winForeground solid solid winFore winFore solid ) + ( display hilite8 stipple0 solid magenta magenta solid ) + ( display y4 stipple0 solid yellow yellow solid ) + ( display Pselect dots1 solid brown brown outlineStipple) + ( display winInactiveBanner solid solid winColor4 winColor4 solid ) + ( display designFlow9 stipple1 lineStyle0 orange orange outlineStipple) + ( display winButton solid solid winFore winFore solid ) + ( display y5 stipple0 solid green green solid ) + ( display hiz stipple0 solid orange orange solid ) + ( display drive stipple0 solid blue blue solid ) + ( display wireFlt stipple0 dashed red red solid ) + ( display instanceLbl stipple0 solid gold gold solid ) + ( display P2ConNet x lineStyle0 orange orange outlineStipple) + ( display designFlow8 stipple1 lineStyle0 navy navy outlineStipple) + ( display y6 stipple0 solid blue blue solid ) + ( display PwellNet dots4 lineStyle0 slate slate outlineStipple) + ( display P1Con solid solid red red solid ) + ( display CapWell dagger solid slate slate outlineStipple) + ( display y7 stipple0 solid purple purple solid ) + ( display ViaX solid solid magenta magenta solid ) + ( display HR x solid chocolate winColor2 outlineStipple) + ( display HRnet x solid chocolate winColor2 outlineStipple) +) diff --git a/technology/scn3me_subm/tf/glade_scn3me_subm.py b/technology/scn3me_subm/tf/glade_scn3me_subm.py new file mode 100644 index 00000000..d2f9aa7e --- /dev/null +++ b/technology/scn3me_subm/tf/glade_scn3me_subm.py @@ -0,0 +1,7 @@ +import os +CWD = os.environ.get("OPENRAM_TECH") + "/scn3me_subm/tf" +ui().importCds("default", CWD+"/display.drf", CWD+"/mosis.tf", 1000, 1, CWD+"/layers.map") + + + + diff --git a/technology/scn3me_subm/tf/layers.map b/technology/scn3me_subm/tf/layers.map new file mode 100644 index 00000000..d10d5f2d --- /dev/null +++ b/technology/scn3me_subm/tf/layers.map @@ -0,0 +1,16 @@ +Pwell drawing 41 0 +Nwell drawing 42 0 +Active drawing 43 0 +Poly1 drawing 46 0 +Pselect drawing 45 0 +Nselect drawing 44 0 +contact drawing 25 0 +P1Con drawing 47 0 +ActX drawing 48 0 +Metal1 drawing 49 0 +Via drawing 50 0 +Metal2 drawing 51 0 +Via2 drawing 61 0 +Metal3 drawing 62 0 +Glass drawing 52 0 +text drawing 83 0 diff --git a/technology/scn3me_subm/tf/mosis.tf b/technology/scn3me_subm/tf/mosis.tf new file mode 100644 index 00000000..759221f1 --- /dev/null +++ b/technology/scn3me_subm/tf/mosis.tf @@ -0,0 +1,848 @@ +; Generated on Sep 28 16:05:23 1998 +; with @(#)$CDS: icfb.exe version 4.4.1 06/17/98 23:40 (cds10067) $ +; +; Matt Clapp fixed: October 10, 2002 +; added via devices, deleted useless app-specific crap, +; added lxExtractRules so undo in layout editor doesn't +; complain. + + +;******************************** +; LAYER DEFINITION +;******************************** + +layerDefinitions( + techLayers( + ;( LayerName Layer# Abbreviation ) + ;( --------- ------ ------------ ) + ;User-Defined Layers: + ( P2Con 3 P2Con ) + ( Poly2 7 Poly2 ) + ( Pbase 10 Pbase ) + ( Resistor 16 Resisto ) + ( Capacitor 17 Capacit ) + ( Diode 18 Diode ) + ( SiBlock 29 SiBlock ) + ( HR 34 HR ) + ( Pwell 41 Pwell ) + ( Nwell 42 Nwell ) + ( Active 43 Active ) + ( Pselect 44 Pselect ) + ( Nselect 45 Nselect ) + ( Poly1 46 Poly1 ) + ( P1Con 47 P1Con ) + ( ActX 48 ActX ) + ( Metal1 49 Metal1 ) + ( Via 50 Via ) + ( Metal2 51 Metal2 ) + ( Glass 52 Glass ) + ( CapWell 59 CapWell ) + ( XP 60 XP ) + ( Via2 61 Via2 ) + ( Metal3 62 Metal3 ) + ( A1 80 A1 ) + ( A2 81 A2 ) + ( comment 117 comment ) + ;System-Reserved Layers: + ( Unrouted 200 Unroute ) + ( Row 201 Row ) + ( Group 202 Group ) + ( Cannotoccupy 203 Cannoto ) + ( Canplace 204 Canplac ) + ( hardFence 205 hardFen ) + ( softFence 206 softFen ) + ( y0 207 y0 ) + ( y1 208 y1 ) + ( y2 209 y2 ) + ( y3 210 y3 ) + ( y4 211 y4 ) + ( y5 212 y5 ) + ( y6 213 y6 ) + ( y7 214 y7 ) + ( y8 215 y8 ) + ( y9 216 y9 ) + ( designFlow 217 designF ) + ( stretch 218 stretch ) + ( edgeLayer 219 edgeLay ) + ( changedLayer 220 changed ) + ( unset 221 unset ) + ( unknown 222 unknown ) + ( spike 223 spike ) + ( hiz 224 hiz ) + ( resist 225 resist ) + ( drive 226 drive ) + ( supply 227 supply ) + ( wire 228 wire ) + ( pin 229 pin ) + ( text 230 text ) + ( device 231 device ) + ( border 232 border ) + ( snap 233 snap ) + ( align 234 align ) + ( prBoundary 235 prBound ) + ( instance 236 instanc ) + ( annotate 237 annotat ) + ( marker 238 marker ) + ( select 239 select ) + ( grid 251 grid ) + ( axis 252 axis ) + ( hilite 253 hilite ) + ( background 254 backgro ) + ) ;techLayers + + techPurposes( + ;( PurposeName Purpose# Abbreviation ) + ;( ----------- -------- ------------ ) + ;User-Defined Purposes: + ;System-Reserved Purposes: + ( warning 234 wng ) + ( tool1 235 tl1 ) + ( tool0 236 tl0 ) + ( label 237 lbl ) + ( flight 238 flt ) + ( error 239 err ) + ( annotate 240 ant ) + ( drawing1 241 dr1 ) + ( drawing2 242 dr2 ) + ( drawing3 243 dr3 ) + ( drawing4 244 dr4 ) + ( drawing5 245 dr5 ) + ( drawing6 246 dr6 ) + ( drawing7 247 dr7 ) + ( drawing8 248 dr8 ) + ( drawing9 249 dr9 ) + ( boundary 250 bnd ) + ( pin 251 pin ) + ( drawing 252 drw ) + ( net 253 net ) + ( cell 254 cel ) + ( all 255 all ) + ) ;techPurposes + + techLayerPurposePriorities( + ;layers are ordered from lowest to highest priority + ; (higher priority is drawn on top of lower priority) + ;( LayerName Purpose ) + ;( --------- ------- ) + ( background drawing ) + ( grid drawing ) + ( grid drawing1 ) + ( Nwell drawing ) + ( Pwell drawing ) + ( CapWell drawing ) + ( Pselect drawing ) + ( Nselect drawing ) + ( Active drawing ) + ( ActX drawing ) + ( SiBlock drawing ) + ( HR drawing ) + ( Poly1 drawing ) + ( P1Con drawing ) + ( Poly2 drawing ) + ( P2Con drawing ) + ( Metal1 drawing ) + ( Via drawing ) + ( Metal2 drawing ) + ( Via2 drawing ) + ( Metal3 drawing ) + ( annotate drawing ) + ( annotate drawing1 ) + ( annotate drawing2 ) + ( annotate drawing3 ) + ( annotate drawing4 ) + ( annotate drawing5 ) + ( annotate drawing6 ) + ( annotate drawing7 ) + ( annotate drawing8 ) + ( annotate drawing9 ) + ( Poly1 pin ) + ( Metal1 pin ) + ( Metal2 pin ) + ( Metal3 pin ) + ( Glass drawing ) + ( XP drawing ) + ( prBoundary drawing ) + ( prBoundary boundary ) + ( instance drawing ) + ( prBoundary label ) + ( instance label ) + ( Row drawing ) + ( Nwell net ) + ( align drawing ) + ( Pwell net ) + ( CapWell net ) + ( hardFence drawing ) + ( Active net ) + ( softFence drawing ) + ( Row label ) + ( Group drawing ) + ( Group label ) + ( Cannotoccupy drawing ) + ( Cannotoccupy boundary ) + ( Canplace drawing ) + ( ActX net ) + ( A2 drawing ) + ( A1 drawing ) + ( comment drawing ) + ( border drawing ) + ( Pselect net ) + ( Nselect net ) + ( SiBlock net ) + ( HR net ) + ( wire drawing ) + ( Poly1 net ) + ( wire label ) + ( P1Con net ) + ( wire flight ) + ( Metal1 net ) + ( device annotate ) + ( Metal2 net ) + ( device label ) + ( Via net ) + ( Metal3 net ) + ( Via2 net ) + ( pin label ) + ( text drawing ) + ( pin drawing ) + ( text drawing1 ) + ( pin annotate ) + ( device drawing ) + ( axis drawing ) + ( edgeLayer drawing ) + ( edgeLayer pin ) + ( snap drawing ) + ( stretch drawing ) + ( y0 drawing ) + ( y1 drawing ) + ( y2 drawing ) + ( y3 drawing ) + ( y4 drawing ) + ( y5 drawing ) + ( y6 drawing ) + ( y7 drawing ) + ( y8 drawing ) + ( y9 drawing ) + ( hilite drawing ) + ( hilite drawing1 ) + ( hilite drawing2 ) + ( hilite drawing3 ) + ( hilite drawing4 ) + ( hilite drawing5 ) + ( hilite drawing6 ) + ( hilite drawing7 ) + ( hilite drawing8 ) + ( hilite drawing9 ) + ( select drawing ) + ( drive drawing ) + ( hiz drawing ) + ( resist drawing ) + ( spike drawing ) + ( supply drawing ) + ( unknown drawing ) + ( unset drawing ) + ( designFlow drawing ) + ( designFlow drawing1 ) + ( designFlow drawing2 ) + ( designFlow drawing3 ) + ( designFlow drawing4 ) + ( designFlow drawing5 ) + ( designFlow drawing6 ) + ( designFlow drawing7 ) + ( designFlow drawing8 ) + ( designFlow drawing9 ) + ( changedLayer tool0 ) + ( changedLayer tool1 ) + ( marker warning ) + ( marker error ) + ( device drawing1 ) + ( Pbase drawing ) + ( Pbase net ) + ( Resistor net ) + ( Resistor drawing ) + ( Capacitor net ) + ( Capacitor drawing ) + ( Diode net ) + ( Diode drawing ) + ( Poly2 net ) + ( P2Con net ) + ( device drawing2 ) + ( Unrouted drawing ) + ( text drawing2 ) + ( Unrouted drawing1 ) + ( Unrouted drawing2 ) + ( Unrouted drawing3 ) + ( Unrouted drawing4 ) + ( Unrouted drawing5 ) + ( Unrouted drawing6 ) + ( Unrouted drawing7 ) + ( Unrouted drawing8 ) + ( Unrouted drawing9 ) + ) ;techLayerPurposePriorities + + techDisplays( + ;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid ) + ;( --------- ------- ------ --- --- --------- ------- ----- ) + ( background drawing background t nil nil nil nil ) + ( grid drawing grid t nil nil nil nil ) + ( grid drawing1 grid1 t nil nil nil nil ) + ( Nwell drawing Nwell t t t t t ) + ( Pwell drawing Pwell t t t t nil ) + ( Active drawing Active t t t t t ) + ( ActX drawing ActX t t t t t ) + ( Pselect drawing Pselect t t t t t ) + ( Nselect drawing Nselect t t t t t ) + ( SiBlock drawing SiBlock t t t t t ) + ( HR drawing HR t t t t t ) + ( CapWell drawing CapWell t t t t t ) + ( Poly1 drawing Poly1 t t t t t ) + ( P1Con drawing P1Con t t t t t ) + ( Metal1 drawing Metal1 t t t t t ) + ( Via drawing Via t t t t t ) + ( Metal2 drawing Metal2 t t t t t ) + ( annotate drawing annotate t t nil t nil ) + ( annotate drawing1 annotate1 t t nil t nil ) + ( annotate drawing2 annotate2 t t nil t nil ) + ( annotate drawing3 annotate3 t t nil t nil ) + ( annotate drawing4 annotate4 t t nil t nil ) + ( annotate drawing5 annotate5 t t nil t nil ) + ( annotate drawing6 annotate6 t t nil t nil ) + ( annotate drawing7 annotate7 t t nil t nil ) + ( annotate drawing8 annotate8 t t nil t nil ) + ( annotate drawing9 annotate9 t t nil t nil ) + ( Via2 drawing Via2 t t t t t ) + ( Metal3 drawing Metal3 t t t t t ) + ( Glass drawing Glass t t t nil t ) + ( XP drawing XP t t t nil t ) + ( Metal1 pin Metal1Pin t t t nil t ) + ( Metal2 pin Metal2Pin t t t nil t ) + ( Metal3 pin Metal3Pin t t t nil t ) + ( Poly1 pin Poly1Pin t t t nil t ) + ( prBoundary drawing prBoundary t t nil t nil ) + ( prBoundary boundary prBoundaryBnd t t nil t nil ) + ( instance drawing instance t t nil t t ) + ( prBoundary label prBoundaryLbl t t t t nil ) + ( instance label instanceLbl t t t t nil ) + ( Row drawing Row t t t t nil ) + ( Nwell net NwellNet t t t nil nil ) + ( align drawing align t t nil t nil ) + ( Pwell net PwellNet t t t nil nil ) + ( CapWell net CapWellNet t t t nil nil ) + ( SiBlock net SiBlockNet t t t nil nil ) + ( HR net HRnet t t t nil nil ) + ( hardFence drawing hardFence t t t t nil ) + ( Active net ActiveNet t t t nil nil ) + ( softFence drawing softFence t t t t nil ) + ( Row label RowLbl t t t t nil ) + ( Group drawing Group t t t t nil ) + ( Group label GroupLbl t t t t nil ) + ( Cannotoccupy drawing Cannotoccupy t t t t nil ) + ( Cannotoccupy boundary CannotoccupyBnd t t t t nil ) + ( Canplace drawing Canplace t t t t nil ) + ( ActX net ActXNet t t t nil nil ) + ( A2 drawing A2 t t t t nil ) + ( A1 drawing A1 t t t t nil ) + ( comment drawing comment t t t t nil ) + ( border drawing border t t t t nil ) + ( Pselect net PselectNet t t t nil nil ) + ( Nselect net NselectNet t t t nil nil ) + ( wire drawing wire t t t t nil ) + ( Poly1 net Poly1Net t t t nil nil ) + ( wire label wireLbl t t t t nil ) + ( P1Con net P1ConNet t t t nil nil ) + ( wire flight wireFlt t t t t nil ) + ( Metal1 net Metal1Net t t t nil nil ) + ( device annotate deviceAnt t t t t nil ) + ( Metal2 net Metal2Net t t t nil nil ) + ( Metal3 net Metal3Net t t t nil nil ) + ( device label deviceLbl t t t t nil ) + ( Via net ViaNet t t t nil nil ) + ( Via2 net Via2Net t t t nil nil ) + ( pin label pinLbl t t t t nil ) + ( text drawing text t t t t t ) + ( pin drawing pin t t t t nil ) + ( text drawing1 text1 t t t t nil ) + ( pin annotate pinAnt t t t t nil ) + ( device drawing device t t t t nil ) + ( axis drawing axis t t t t nil ) + ( edgeLayer drawing edgeLayer t t nil t nil ) + ( edgeLayer pin edgeLayerPin t t nil t nil ) + ( snap drawing snap t t nil t nil ) + ( stretch drawing stretch t t nil t nil ) + ( y0 drawing y0 t t nil t nil ) + ( y1 drawing y1 t t nil t nil ) + ( y2 drawing y2 t t nil t nil ) + ( y3 drawing y3 t t nil t nil ) + ( y4 drawing y4 t t nil t nil ) + ( y5 drawing y5 t t nil t nil ) + ( y6 drawing y6 t t nil t nil ) + ( y7 drawing y7 t t nil t nil ) + ( y8 drawing y8 t t nil t nil ) + ( y9 drawing y9 t t nil t nil ) + ( hilite drawing hilite t t nil t nil ) + ( hilite drawing1 hilite1 t t t t nil ) + ( hilite drawing2 hilite2 t t nil t nil ) + ( hilite drawing3 hilite3 t t t t nil ) + ( hilite drawing4 hilite4 t t t t nil ) + ( hilite drawing5 hilite5 t t t t nil ) + ( hilite drawing6 hilite6 t t t t nil ) + ( hilite drawing7 hilite7 t t t t nil ) + ( hilite drawing8 hilite8 t t t t nil ) + ( hilite drawing9 hilite9 t t t t nil ) + ( select drawing select t t nil t nil ) + ( drive drawing drive t t t t nil ) + ( hiz drawing hiz t t t t nil ) + ( resist drawing resist t t t t nil ) + ( spike drawing spike t t t t nil ) + ( supply drawing supply t t t t nil ) + ( unknown drawing unknown t t t t nil ) + ( unset drawing unset t t t t nil ) + ( designFlow drawing designFlow t t t nil nil ) + ( designFlow drawing1 designFlow1 t t t nil nil ) + ( designFlow drawing2 designFlow2 t t t nil nil ) + ( designFlow drawing3 designFlow3 t t t nil nil ) + ( designFlow drawing4 designFlow4 t t t nil nil ) + ( designFlow drawing5 designFlow5 t t t nil nil ) + ( designFlow drawing6 designFlow6 t t t nil nil ) + ( designFlow drawing7 designFlow7 t t t nil nil ) + ( designFlow drawing8 designFlow8 t t t nil nil ) + ( designFlow drawing9 designFlow9 t t t nil nil ) + ( changedLayer tool0 changedLayerTl0 nil nil nil nil nil ) + ( changedLayer tool1 changedLayerTl1 nil nil t nil nil ) + ( marker warning markerWarn t t t t nil ) + ( marker error markerErr t t t t nil ) + ( device drawing1 device1 t t t t nil ) + ( Poly2 net Poly2Net t t t nil nil ) + ( Poly2 drawing Poly2 t t t t t ) + ( P2Con net P2ConNet t t t nil nil ) + ( P2Con drawing P2Con t t t t t ) + ( Pbase net PbaseNet t t t nil nil ) + ( Pbase drawing Pbase t t t t t ) + ( Resistor net ResistorNet t t t nil nil ) + ( Resistor drawing Resistor t t t t t ) + ( Capacitor net CapacitorNet t t t nil nil ) + ( Capacitor drawing Capacitor t t t t t ) + ( Diode net DiodeNet t t t nil nil ) + ( Diode drawing Diode t t t t t ) + ( device drawing2 device2 t t t t nil ) + ( Unrouted drawing Unrouted t t t t nil ) + ( text drawing2 text2 t t t t nil ) + ( Unrouted drawing1 Unrouted1 t t t t nil ) + ( Unrouted drawing2 Unrouted2 t t t t nil ) + ( Unrouted drawing3 Unrouted3 t t t t nil ) + ( Unrouted drawing4 Unrouted4 t t t t nil ) + ( Unrouted drawing5 Unrouted5 t t t t nil ) + ( Unrouted drawing6 Unrouted6 t t t t nil ) + ( Unrouted drawing7 Unrouted7 t t t t nil ) + ( Unrouted drawing8 Unrouted8 t t t t nil ) + ( Unrouted drawing9 Unrouted9 t t t t nil ) + ) ;techDisplays + +; I don't think the following is necessary (or used!) +techLayerProperties( +;( PropName Layer1 [ Layer2 ] PropValue ) + ( contactLimit P2Con 10000 ) + ( eqPinLimit P2Con 10000 ) + ( horizontalJogLength P2Con 2147483648.000000 ) + ( routingGrid P2Con 1.000000 ) + ( verticalJogLength P2Con 2147483648.000000 ) + ( routingGrid Poly2 1.000000 ) + ( contactLimit Active 10000 ) + ( eqPinLimit Active 10000 ) + ( horizontalJogLength Active 2147483648.000000 ) + ( routingGrid Active 1.000000 ) + ( verticalJogLength Active 2147483648.000000 ) + ( routingGrid Poly1 1.000000 ) + ( contactLimit P1Con 10000 ) + ( eqPinLimit P1Con 10000 ) + ( horizontalJogLength P1Con 2147483648.000000 ) + ( routingGrid P1Con 1.000000 ) + ( verticalJogLength P1Con 2147483648.000000 ) + ( contactLimit ActX 10000 ) + ( eqPinLimit ActX 10000 ) + ( horizontalJogLength ActX 2147483648.000000 ) + ( routingGrid ActX 1.000000 ) + ( verticalJogLength ActX 2147483648.000000 ) + ( routingGrid Metal1 1.000000 ) + ( contactLimit Via 10000 ) + ( eqPinLimit Via 10000 ) + ( horizontalJogLength Via 2147483648.000000 ) + ( routingGrid Via 1.000000 ) + ( verticalJogLength Via 2147483648.000000 ) + ( routingGrid Metal2 1.000000 ) +) + +) ;layerDefinitions + + +;******************************** +; DEVICE RULES +;******************************** + +devices( + tcCreateCDSDeviceClass() + + symContactDevice( + ;( deviceName viaLayer viaPurpose + ( VIA Via drawing + + ; layer1 purpose1 [implant1] + Metal1 drawing + + ; layer2 purpose2 [implant2] + Metal2 drawing + + ; width length [( row column xPitch yPitch xBias yBias )] + ; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ ) + 2 2 + + ; encLayer1 encLayer2 legalRegion ) + 1 1 _NA_) + ) ;symContactDevice + + symContactDevice( + ;( deviceName viaLayer viaPurpose + ( VIA2 Via2 drawing + + ; layer1 purpose1 [implant1] + Metal2 drawing + + ; layer2 purpose2 [implant2] + Metal3 drawing + + ; width length [( row column xPitch yPitch xBias yBias )] + ; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ ) + 2 2 + + ; encLayer1 encLayer2 legalRegion ) + 1 2 _NA_) + ) ;symContactDevice + +) ;devices + + +;******************************** +; LAYER RULES +;******************************** + +layerRules( + streamLayers( + ;( layer streamNumber dataType translate ) + ;( ----- ------------ -------- --------- ) + ( ("background" "drawing") 0 0 nil ) + ( ("grid" "drawing") 0 0 nil ) + ( ("grid" "drawing1") 0 0 nil ) + ( ("Nwell" "drawing") 42 0 t ) + ( ("Pwell" "drawing") 41 0 t ) + ( ("Active" "drawing") 43 0 t ) + ( ("ActX" "drawing") 48 0 t ) + ( ("Pselect" "drawing") 44 0 t ) + ( ("Nselect" "drawing") 45 0 t ) + ( ("Poly1" "drawing") 46 0 t ) + ( ("P1Con" "drawing") 47 0 t ) + ( ("Metal1" "drawing") 49 0 t ) + ( ("Metal2" "drawing") 51 0 t ) + ( ("annotate" "drawing") 0 0 nil ) + ( ("annotate" "drawing1") 0 0 nil ) + ( ("annotate" "drawing2") 0 0 nil ) + ( ("annotate" "drawing3") 0 0 nil ) + ( ("annotate" "drawing4") 0 0 nil ) + ( ("annotate" "drawing5") 0 0 nil ) + ( ("annotate" "drawing6") 0 0 nil ) + ( ("annotate" "drawing7") 0 0 nil ) + ( ("annotate" "drawing8") 0 0 nil ) + ( ("annotate" "drawing9") 0 0 nil ) + ( ("Via" "drawing") 50 0 t ) + ( ("Glass" "drawing") 52 0 t ) + ( ("XP" "drawing") 60 0 t ) + ( ("Metal2" "pin") 0 0 nil ) + ( ("Poly1" "pin") 0 0 nil ) + ( ("prBoundary" "drawing") 0 0 nil ) + ( ("Metal1" "pin") 0 0 nil ) + ( ("prBoundary" "boundary") 0 0 nil ) + ( ("instance" "drawing") 246 0 nil ) + ( ("instance" "label") 0 0 nil ) + ( ("Nwell" "net") 0 0 nil ) + ( ("align" "drawing") 0 0 nil ) + ( ("Pwell" "net") 0 0 nil ) + ( ("hardFence" "drawing") 0 0 nil ) + ( ("Active" "net") 0 0 nil ) + ( ("softFence" "drawing") 0 0 nil ) + ( ("ActX" "net") 0 0 nil ) + ( ("A2" "drawing") 5 0 nil ) + ( ("A1" "drawing") 2 0 nil ) + ( ("comment" "drawing") 0 0 nil ) + ( ("border" "drawing") 0 0 nil ) + ( ("Pselect" "net") 0 0 nil ) + ( ("Nselect" "net") 0 0 nil ) + ( ("wire" "drawing") 0 0 nil ) + ( ("Poly1" "net") 0 0 nil ) + ( ("P1Con" "net") 0 0 nil ) + ( ("Metal1" "net") 0 0 nil ) + ( ("Metal2" "net") 0 0 nil ) + ( ("device" "label") 0 0 nil ) + ( ("Via" "net") 0 0 nil ) + ( ("pin" "label") 0 0 nil ) + ( ("text" "drawing") 63 0 t ) + ( ("pin" "drawing") 0 0 nil ) + ( ("device" "drawing") 0 0 nil ) + ( ("axis" "drawing") 0 0 nil ) + ( ("edgeLayer" "drawing") 0 0 nil ) + ( ("edgeLayer" "pin") 0 0 nil ) + ( ("snap" "drawing") 0 0 nil ) + ( ("stretch" "drawing") 0 0 nil ) + ( ("y0" "drawing") 0 0 nil ) + ( ("y1" "drawing") 0 0 nil ) + ( ("y2" "drawing") 0 0 nil ) + ( ("y3" "drawing") 0 0 nil ) + ( ("y4" "drawing") 0 0 nil ) + ( ("y5" "drawing") 0 0 nil ) + ( ("y6" "drawing") 0 0 nil ) + ( ("y7" "drawing") 0 0 nil ) + ( ("y8" "drawing") 0 0 nil ) + ( ("y9" "drawing") 0 0 nil ) + ( ("hilite" "drawing") 0 0 nil ) + ( ("hilite" "drawing2") 0 0 nil ) + ( ("select" "drawing") 0 0 nil ) + ( ("drive" "drawing") 0 0 nil ) + ( ("hiz" "drawing") 0 0 nil ) + ( ("resist" "drawing") 0 0 nil ) + ( ("spike" "drawing") 0 0 nil ) + ( ("supply" "drawing") 0 0 nil ) + ( ("unknown" "drawing") 0 0 nil ) + ( ("unset" "drawing") 0 0 nil ) + ( ("changedLayer" "tool0") 0 0 nil ) + ( ("Resistor" "net") 0 0 nil ) + ( ("Resistor" "drawing") 0 0 nil ) + ( ("Capacitor" "net") 0 0 nil ) + ( ("Capacitor" "drawing") 0 0 nil ) + ( ("Diode" "net") 0 0 nil ) + ( ("Diode" "drawing") 0 0 nil ) + ( ("Poly2" "net") 0 0 nil ) + ( ("Poly2" "drawing") 0 0 nil ) + ( ("P2Con" "net") 0 0 nil ) + ( ("P2Con" "drawing") 0 0 nil ) + ( ("Pbase" "drawing") 0 0 nil ) + ( ("Pbase" "net") 0 0 nil ) + ( P2Con 0 0 nil ) + ( Poly2 0 0 nil ) + ( Pwell 0 0 nil ) + ( Nwell 0 0 nil ) + ( Active 0 0 nil ) + ( Pselect 0 0 nil ) + ( Nselect 0 0 nil ) + ( Poly1 0 0 nil ) + ( P1Con 0 0 nil ) + ( ActX 0 0 nil ) + ( Metal1 0 0 nil ) + ( Via 0 0 nil ) + ( Metal2 0 0 nil ) + ( Glass 0 0 nil ) + ( XP 0 0 nil ) + ( ("Via2" "drawing") 50 0 t ) + ( ("Via2" "net") 0 0 nil ) + ( ("Metal3" "drawing") 50 0 t ) + ( ("Metal3" "net") 0 0 nil ) + ( ("Metal3" "pin") 0 0 nil ) + ( ("CapWell" "drawing") 0 0 nil ) + ( ("CapWell" "net") 0 0 nil ) + ( ("SiBlock" "drawing") 0 0 nil ) + ( ("SiBlock" "net") 0 0 nil ) + ( ("HR" "drawing") 0 0 nil ) + ( ("HR" "net") 0 0 nil ) + ) ;streamLayers + + viaLayers( + ;( layer1 viaLayer layer2 ) + ;( ------ -------- ------ ) + ( Metal2 Via2 Metal3 ) + ( Metal1 Via Metal2 ) + ( Active ActX Poly1 ) + ( Poly1 P1Con Metal1 ) + ( Poly2 P2Con Metal1 ) + ) ;viaLayers + +) ;layerRules + + +;******************************** +; PHYSICAL RULES +;******************************** + +physicalRules( + orderedSpacingRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( minEnclosure "prBoundary" "Metal1" 0.0 ) + ( minEnclosure "Metal2" "Via" 1.0 ) + ( minEnclosure "Metal1" "Via" 1.0 ) + ( minEnclosure "Metal1" "P1Con" 1.0 ) + ( minEnclosure "Metal1" "ActX" 1.0 ) + ( minEnclosure "Nselect" "Active" 2.0 ) + ( minEnclosure "Pselect" "Active" 2.0 ) + ( minEnclosure "Active" "ActX" 1.0 ) + ( minEnclosure "Pwell" "Active" 5.0 ) + ( minEnclosure "Nwell" "Active" 5.0 ) + ) ;orderedSpacingRules + + spacingRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( minSpacing "P2Con" 2.0 ) + ( minSpacing "Poly2" 3.0 ) + ( minSpacing "Pwell" 9.0 ) + ( minSpacing "Nwell" 9.0 ) + ( minSpacing "Active" 3.0 ) + ( minSpacing "Pselect" 2.0 ) + ( minSpacing "Nselect" 2.0 ) + ( minSpacing "Poly1" 2.0 ) + ( minSpacing "P1Con" 2.0 ) + ( minSpacing "ActX" 2.0 ) + ( minSpacing "Metal1" 3.0 ) + ( minSpacing "Via" 3.0 ) + ( minSpacing "Via2" 3.0 ) + ( minSpacing "Metal2" 3.0 ) + ( minSpacing "Metal3" 4.0 ) + ( minSpacing "Glass" 75.0 ) + ( minSpacing "XP" 100.0 ) + ( minSpacing "Metal2" 4.0 ) + ( minSpacing "P1Con" "Via" 2.0 ) + ( minSpacing "ActX" "Via" 2.0 ) + ( minSpacing "ActX" "P2Con" 2.0 ) + ( minSpacing "Poly2" "P2Con" 4.0 ) + ( minSpacing "Poly1" "P1Con" 4.0 ) + ( minSpacing "ActX" "P1Con" 2.0 ) + ( minSpacing "Active" "P1Con" 2.0 ) + ( minSpacing "Active" "Poly2" 2.0 ) + ( minSpacing "Poly1" "Poly2" 2.0 ) + ( minSpacing "Active" "Poly1" 2.0 ) + ( minSpacing "ActX" "Poly1" 2.0 ) + ( minSpacing "Pselect" "Nselect" 0.0 ) + ( minSpacing "Nwell" "Pwell" 9.0 ) + ( minWidth "P2Con" 2.0 ) + ( minWidth "Poly2" 3.0 ) + ( minWidth "Pwell" 10.0 ) + ( minWidth "Nwell" 10.0 ) + ( minWidth "Active" 3.0 ) + ( minWidth "Pselect" 2.0 ) + ( minWidth "Nselect" 2.0 ) + ( minWidth "Poly1" 2.0 ) + ( minWidth "P1Con" 2.0 ) + ( minWidth "ActX" 2.0 ) + ( minWidth "Metal1" 4.0 ) + ( minWidth "Via" 2.0 ) + ( minWidth "Metal2" 4.0 ) + ( minWidth "Glass" 75.0 ) + ( minWidth "XP" 100.0 ) + ( minWidth "Metal3" 6.0 ) + ) ;spacingRules + + mfgGridResolution( + ( 1.000000 ) + ) ;mfgGridResolution + +) ;physicalRules + + +;******************************** +; ELECTRICAL RULES +;******************************** + +electricalRules( + characterizationRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( areaCap "P2Con" 0.0 ) + ( areaCap "Poly2" 0.0 ) + ( areaCap "Active" 0.0 ) + ( areaCap "Poly1" 6e-05 ) + ( areaCap "P1Con" 0.0 ) + ( areaCap "ActX" 0.0 ) + ( areaCap "Metal1" 2.6e-05 ) + ( areaCap "Via" 0.0 ) + ( areaCap "Metal2" 1.6e-05 ) + ( edgeCapacitance "P2Con" 0.0 ) + ( edgeCapacitance "Poly2" 0.0 ) + ( edgeCapacitance "Active" 0.0 ) + ( edgeCapacitance "Poly1" 0.0 ) + ( edgeCapacitance "P1Con" 0.0 ) + ( edgeCapacitance "ActX" 0.0 ) + ( edgeCapacitance "Metal1" 0.0 ) + ( edgeCapacitance "Via" 0.0 ) + ( edgeCapacitance "Metal2" 0.0 ) + ( sheetRes "P2Con" 0.0 ) + ( sheetRes "Poly2" 0.0 ) + ( sheetRes "Active" 0.0 ) + ( sheetRes "Poly1" 23.0 ) + ( sheetRes "P1Con" 0.0 ) + ( sheetRes "ActX" 0.0 ) + ( sheetRes "Metal1" 0.04 ) + ( sheetRes "Via" 0.0 ) + ( sheetRes "Metal2" 0.07 ) + ( currentDensity "P2Con" 1.0 ) + ( currentDensity "Poly2" 1.0 ) + ( currentDensity "Active" 1.0 ) + ( currentDensity "Poly1" 1.0 ) + ( currentDensity "P1Con" 1.0 ) + ( currentDensity "ActX" 1.0 ) + ( currentDensity "Metal1" 1.0 ) + ( currentDensity "Via" 1.0 ) + ( currentDensity "Metal2" 1.0 ) + ) ;characterizationRules + +) ;electricalRules + + +;******************************** +; LAYOUT EDITOR RULES +;******************************** +; specifies the ordering of the layers in the LSW + +leRules( + leLswLayers( + ;( layer purpose ) + ; ----- ------- ) + ( Nwell drawing ) + ( Pselect drawing ) + ( Nselect drawing ) + ( Active drawing ) + ( ActX drawing ) + ( Poly1 drawing ) + ( P1Con drawing ) + ( Metal1 drawing ) + ( Via drawing ) + ( Metal2 drawing ) + ( Via2 drawing ) + ( Metal3 drawing ) + ( Poly1 pin ) + ( Metal1 pin ) + ( Metal2 pin ) + ( Metal3 pin ) + ( Poly2 drawing ) + ( P2Con drawing ) + ( instance drawing ) + ( text drawing ) + ( CapWell drawing ) + ( SiBlock drawing ) + ( HR drawing ) + ( Pbase drawing ) + ( Resistor drawing ) + ( Capacitor drawing ) + ( Diode drawing ) + ( Glass drawing ) + ( XP drawing ) + + ) ;leLswLayers +) ;leRules + + +;******************************** +; VIRTUOSO XL RULES +;******************************** +; specifies the ordering of the layers in the LSW + +lxRules( + lxExtractLayers( + (Metal1 Metal2 Metal3) + ) ;lxExtractLayers +) ;lxRules +