merging changes in bitcell.py

This commit is contained in:
Michael Timothy Grimes
2018-04-03 09:46:12 -07:00
48 changed files with 6710 additions and 59 deletions
@@ -82,7 +82,7 @@ cell (sram_2_16_1_freepdk45){
leakage_power () {
when : "CSb";
value : 0;
value : 0.000173;
}
cell_leakage_power : 0;
bus(DATA){
@@ -298,19 +298,19 @@ cell (sram_2_16_1_freepdk45){
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0");
values("0.065526962224");
}
fall_power(scalar){
values("0.0");
values("0.065526962224");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0");
values("0.065526962224");
}
fall_power(scalar){
values("0.0");
values("0.065526962224");
}
}
internal_power(){
@@ -82,7 +82,7 @@ cell (sram_2_16_1_scn3me_subm){
leakage_power () {
when : "CSb";
value : 0;
value : 0.000173;
}
cell_leakage_power : 0;
bus(DATA){
@@ -298,19 +298,19 @@ cell (sram_2_16_1_scn3me_subm){
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0");
values("10.9314668117");
}
fall_power(scalar){
values("0.0");
values("10.9314668117");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0");
values("10.9314668117");
}
fall_power(scalar){
values("0.0");
values("10.9314668117");
}
}
internal_power(){