merging changes in bitcell.py

compiler/modules/bank.py

@@ -1228,3 +1228,4 @@ class bank(design.design):
         result = msf_addr_delay + decoder_delay + word_driver_delay \
                  + bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay
         return result
+        

compiler/modules/bitcell.py

@@ -34,7 +34,8 @@ class bitcell(design.design):
         c_para = spice["min_tx_drain_c"]
         result = self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew, swing = swing)
         return result
-    
+   
+ 
     def list_bitcell_pins(self, col, row):
         # Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array
         bitcell_pins = ["bl[{0}]".format(col),
@@ -56,4 +57,12 @@ class bitcell(design.design):
         column_pins = ["BL", "BR"]
         return column_pins
         
-    
+    
+    def analytical_power(self, proc, vdd, temp, load):
+        """Bitcell power in nW. Only characterizes leakage."""
+        from tech import spice
+        leakage = spice["bitcell_leakage"]
+        dynamic = 0 #temporary
+        total_power = self.return_power(dynamic, leakage)
+        return total_power
+

compiler/modules/bitcell_array.py

@@ -179,6 +179,25 @@ class bitcell_array(design.design):
         #we do not consider the delay over the wire for now
         return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
                                  wl_to_cell_delay.slew)
+                        
+    def analytical_power(self, proc, vdd, temp, load):
+        """Power of Bitcell array and bitline in nW."""
+        from tech import drc
+        
+        # Dynamic Power from Bitline
+        bl_wire = self.gen_bl_wire()
+        cell_load = 2 * bl_wire.return_input_cap() 
+        bl_swing = 0.1 #This should probably be defined in the tech file or input
+        freq = spice["default_event_rate"]
+        bitline_dynamic = bl_swing*cell_load*vdd*vdd*freq #not sure if calculation is correct
+        
+        #Calculate the bitcell power which currently only includes leakage 
+        cell_power = self.cell.analytical_power(proc, vdd, temp, load)
+        
+        #Leakage power grows with entire array and bitlines.
+        total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
+                                        cell_power.leakage * self.column_size * self.row_size)
+        return total_power
 
     def gen_wl_wire(self):
         wl_wire = self.generate_rc_net(int(self.column_size), self.width, drc["minwidth_metal1"])

compiler/modules/control_logic.py

@@ -98,7 +98,7 @@ class control_logic(design.design):
 
         # GAP between main control and replica bitline
         self.replica_bitline_gap = 2*self.m2_pitch
-
+        
 
 
     def add_modules(self):
@@ -688,4 +688,4 @@ class control_logic(design.design):
                            height=pin.height(),
                            width=pin.width())
         
-        
+        

compiler/modules/hierarchical_decoder.py

@@ -494,6 +494,7 @@ class hierarchical_decoder(design.design):
         result = result + z_t_decodeout_delay
         return result
 
+        
     def input_load(self):
         if self.determine_predecodes(self.num_inputs)[1]==0:
             pre = self.pre2_4

compiler/modules/hierarchical_predecode2x4.py

@@ -55,5 +55,6 @@ class hierarchical_predecode2x4(hierarchical_predecode):
 
         return a_t_b_delay + b_t_z_delay + a_t_out_delay
 
+        
     def input_load(self):
         return self.nand.input_load()

compiler/modules/hierarchical_predecode3x8.py

@@ -64,6 +64,5 @@ class hierarchical_predecode3x8(hierarchical_predecode):
         return a_t_b_delay + b_t_z_delay + a_t_out_delay
 
 
-
     def input_load(self):
         return self.nand.input_load()

compiler/modules/ms_flop.py

@@ -26,4 +26,25 @@ class ms_flop(design.design):
         from tech import spice
         result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"])
         return result
+        
+    def analytical_power(self, proc, vdd, temp, load):
+        """Returns dynamic and leakage power. Results in nW"""
+        from tech import spice
+        c_eff = self.calculate_effective_capacitance(load)
+        f = spice["default_event_rate"]
+        power_dyn = c_eff*vdd*vdd*f
+        power_leak = spice["msflop_leakage"]
+        
+        total_power = self.return_power(power_dyn, power_leak)
+        return total_power
+        
+    def calculate_effective_capacitance(self, load):
+        """Computes effective capacitance. Results in fF"""
+        from tech import spice, parameter
+        c_load = load
+        c_para = spice["flop_para_cap"]#ff
+        transistion_prob = spice["flop_transisition_prob"]
+        return transistion_prob*(c_load + c_para) 
 
+        
+        

compiler/modules/ms_flop_array.py

@@ -134,3 +134,4 @@ class ms_flop_array(design.design):
 
     def analytical_delay(self, slew, load=0.0):
         return self.ms.analytical_delay(slew=slew, load=load)
+        

compiler/modules/sense_amp.py

@@ -30,3 +30,8 @@ class sense_amp(design.design):
         result = self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew)
         return self.return_delay(result.delay, result.slew)
 
+    def analytical_power(self, proc, vdd, temp, load):
+        """Returns dynamic and leakage power. Results in nW"""
+        #Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
+        total_power = self.return_power()
+        return total_power

compiler/modules/sense_amp_array.py

@@ -117,3 +117,4 @@ class sense_amp_array(design.design):
 
     def analytical_delay(self, slew, load=0.0):
         return self.amp.analytical_delay(slew=slew, load=load)
+        

compiler/modules/tri_gate.py

@@ -32,7 +32,12 @@ class tri_gate(design.design):
         r = spice["min_tx_r"]
         c_para = spice["min_tx_drain_c"]
         return self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew)
-
+        
+    def analytical_power(self, proc, vdd, temp, load):
+        """Returns dynamic and leakage power. Results in nW"""
+        #Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
+        total_power = self.return_power() 
+        return total_power
 
     def input_load(self):
         return 9*spice["min_tx_gate_c"]

compiler/modules/tri_gate_array.py

@@ -111,3 +111,4 @@ class tri_gate_array(design.design):
 
     def analytical_delay(self, slew, load=0.0):
         return self.tri.analytical_delay(slew = slew, load = load)
+        

compiler/modules/wordline_driver.py

@@ -205,6 +205,7 @@ class wordline_driver(design.design):
         net_t_wl = self.inv.analytical_delay(decode_t_net.slew, load)
 
         return decode_t_net + net_t_wl
-    
+
+        
     def input_load(self):
         return self.nand2.input_load()