From 6a4f6cbbed8c63b80ea7a7f2a6a8dcd2644813a9 Mon Sep 17 00:00:00 2001 From: Eren Dogan Date: Fri, 2 Dec 2022 15:28:06 -0800 Subject: [PATCH] Move sram and sram_config to openram namespace --- __init__.py | 4 ++++ compiler/modules/__init__.py | 2 -- compiler/{modules => }/sram.py | 8 ++++---- compiler/{modules => }/sram_config.py | 0 compiler/tests/18_port_data_16mux_1rw_1r_test.py | 2 +- compiler/tests/18_port_data_16mux_test.py | 2 +- compiler/tests/18_port_data_2mux_1rw_1r_test.py | 2 +- compiler/tests/18_port_data_2mux_test.py | 2 +- compiler/tests/18_port_data_4mux_1rw_1r_test.py | 2 +- compiler/tests/18_port_data_4mux_test.py | 2 +- compiler/tests/18_port_data_8mux_1rw_1r_test.py | 2 +- compiler/tests/18_port_data_8mux_test.py | 2 +- compiler/tests/18_port_data_nomux_1rw_1r_test.py | 2 +- compiler/tests/18_port_data_nomux_test.py | 2 +- compiler/tests/18_port_data_spare_cols_test.py | 2 +- compiler/tests/18_port_data_wmask_1rw_1r_test.py | 2 +- compiler/tests/18_port_data_wmask_test.py | 2 +- compiler/tests/19_multi_bank_test.py | 2 +- compiler/tests/19_pmulti_bank_test.py | 2 +- compiler/tests/19_psingle_bank_test.py | 2 +- compiler/tests/19_single_bank_16mux_1rw_1r_test.py | 2 +- compiler/tests/19_single_bank_16mux_test.py | 2 +- compiler/tests/19_single_bank_1w_1r_test.py | 2 +- compiler/tests/19_single_bank_2mux_1rw_1r_test.py | 2 +- compiler/tests/19_single_bank_2mux_test.py | 2 +- compiler/tests/19_single_bank_4mux_1rw_1r_test.py | 2 +- compiler/tests/19_single_bank_4mux_test.py | 2 +- compiler/tests/19_single_bank_8mux_1rw_1r_test.py | 2 +- compiler/tests/19_single_bank_8mux_test.py | 2 +- compiler/tests/19_single_bank_global_bitline_test.py | 2 +- compiler/tests/19_single_bank_nomux_1rw_1r_test.py | 2 +- compiler/tests/19_single_bank_nomux_test.py | 2 +- compiler/tests/19_single_bank_spare_cols_test.py | 2 +- compiler/tests/19_single_bank_wmask_1rw_1r_test.py | 2 +- compiler/tests/19_single_bank_wmask_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_test.py | 2 +- compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_16mux_test.py | 2 +- .../tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py | 2 +- .../tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_global_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_test.py | 2 +- .../tests/20_sram_1bank_2mux_wmask_spare_cols_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_wmask_test.py | 2 +- compiler/tests/20_sram_1bank_32b_1024_wmask_test.py | 2 +- compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_4mux_test.py | 2 +- compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_8mux_test.py | 2 +- .../tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py | 2 +- compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_nomux_spare_cols_test.py | 2 +- compiler/tests/20_sram_1bank_nomux_test.py | 2 +- .../tests/20_sram_1bank_nomux_wmask_sparecols_test.py | 2 +- compiler/tests/20_sram_1bank_nomux_wmask_test.py | 2 +- compiler/tests/20_sram_1bank_ring_test.py | 2 +- compiler/tests/20_sram_2bank_test.py | 2 +- compiler/tests/21_hspice_delay_test.py | 2 +- compiler/tests/21_model_delay_test.py | 4 ++-- compiler/tests/21_ngspice_delay_extra_rows_test.py | 2 +- compiler/tests/21_ngspice_delay_global_test.py | 2 +- compiler/tests/21_ngspice_delay_test.py | 2 +- compiler/tests/21_regression_delay_test.py | 4 ++-- compiler/tests/21_xyce_delay_test.py | 2 +- compiler/tests/22_psram_1bank_2mux_func_test.py | 2 +- compiler/tests/22_psram_1bank_4mux_func_test.py | 2 +- compiler/tests/22_psram_1bank_8mux_func_test.py | 2 +- compiler/tests/22_psram_1bank_nomux_func_test.py | 2 +- compiler/tests/22_sram_1bank_2mux_func_test.py | 2 +- compiler/tests/22_sram_1bank_2mux_global_func_test.py | 2 +- compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py | 2 +- compiler/tests/22_sram_1bank_4mux_func_test.py | 2 +- compiler/tests/22_sram_1bank_8mux_func_test.py | 2 +- compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py | 2 +- compiler/tests/22_sram_1bank_nomux_func_test.py | 2 +- compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py | 2 +- compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py | 2 +- compiler/tests/22_sram_wmask_func_test.py | 2 +- compiler/tests/23_lib_sram_linear_regression_test.py | 4 ++-- compiler/tests/23_lib_sram_model_corners_test.py | 4 ++-- compiler/tests/23_lib_sram_model_test.py | 4 ++-- compiler/tests/23_lib_sram_prune_test.py | 4 ++-- compiler/tests/23_lib_sram_test.py | 4 ++-- compiler/tests/24_lef_sram_test.py | 4 ++-- compiler/tests/25_verilog_multibank_test.py | 4 ++-- compiler/tests/25_verilog_sram_test.py | 4 ++-- compiler/tests/26_sram_pex_test.py | 2 +- compiler/tests/30_openram_back_end_library_test.py | 2 +- compiler/tests/30_openram_front_end_library_test.py | 2 +- compiler/tests/50_riscv_1k_1rw1r_func_test.py | 2 +- compiler/tests/50_riscv_1k_1rw_func_test.py | 2 +- compiler/tests/50_riscv_1rw1r_func_test.py | 2 +- compiler/tests/50_riscv_1rw1r_phys_test.py | 2 +- compiler/tests/50_riscv_1rw_func_test.py | 2 +- compiler/tests/50_riscv_1rw_phys_test.py | 2 +- compiler/tests/50_riscv_2k_1rw1r_func_test.py | 2 +- compiler/tests/50_riscv_2k_1rw_func_test.py | 2 +- compiler/tests/50_riscv_4k_1rw1r_func_test.py | 2 +- compiler/tests/50_riscv_4k_1rw_func_test.py | 2 +- compiler/tests/50_riscv_512b_1rw1r_func_test.py | 2 +- compiler/tests/50_riscv_512b_1rw_func_test.py | 2 +- compiler/tests/50_riscv_8k_1rw1r_func_test.py | 2 +- compiler/tests/50_riscv_8k_1rw_func_test.py | 2 +- sram_compiler.py | 2 +- 110 files changed, 124 insertions(+), 122 deletions(-) rename compiler/{modules => }/sram.py (97%) rename compiler/{modules => }/sram_config.py (100%) diff --git a/__init__.py b/__init__.py index cda3bec0..cabfc7fa 100644 --- a/__init__.py +++ b/__init__.py @@ -25,3 +25,7 @@ __path__.insert(0, OPENRAM_HOME) # Import everything in globals.py from .globals import * +# Import classes in the "openram" namespace +# sram_config should be imported before sram +from .sram_config import * +from .sram import * diff --git a/compiler/modules/__init__.py b/compiler/modules/__init__.py index 43676426..5d10d3fa 100755 --- a/compiler/modules/__init__.py +++ b/compiler/modules/__init__.py @@ -83,6 +83,4 @@ from .write_driver_array import * from .write_driver import * from .write_mask_and_array import * from .sram_1bank import * -from .sram_config import * -from .sram import * from .internal_base import * diff --git a/compiler/modules/sram.py b/compiler/sram.py similarity index 97% rename from compiler/modules/sram.py rename to compiler/sram.py index 341351e1..66c4c955 100644 --- a/compiler/modules/sram.py +++ b/compiler/sram.py @@ -9,8 +9,7 @@ import os import shutil import datetime from openram import debug -from openram.characterizer import functional -from openram.modules import sram_config as config +from openram import sram_config as config from openram import OPTS, print_time @@ -50,7 +49,7 @@ class sram(): self.name = name - from .sram_1bank import sram_1bank as sram + from openram.modules.sram_1bank import sram_1bank as sram self.s = sram(name, sram_config) @@ -73,7 +72,7 @@ class sram(): def verilog_write(self, name): self.s.verilog_write(name) if self.num_banks != 1: - from .sram_multibank import sram_multibank + from openram.modules.sram_multibank import sram_multibank mb = sram_multibank(self.s) mb.verilog_write(name[:-2] + '_top.v') @@ -95,6 +94,7 @@ class sram(): # Import this at the last minute so that the proper tech file # is loaded and the right tools are selected from openram import verify + from openram.characterizer import functional # Save the spice file start_time = datetime.datetime.now() diff --git a/compiler/modules/sram_config.py b/compiler/sram_config.py similarity index 100% rename from compiler/modules/sram_config.py rename to compiler/sram_config.py diff --git a/compiler/tests/18_port_data_16mux_1rw_1r_test.py b/compiler/tests/18_port_data_16mux_1rw_1r_test.py index de5e92e6..1ba5ccc0 100755 --- a/compiler/tests/18_port_data_16mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_16mux_1rw_1r_test.py @@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_16mux_test.py b/compiler/tests/18_port_data_16mux_test.py index fb2fc6ec..abf5cd5f 100755 --- a/compiler/tests/18_port_data_16mux_test.py +++ b/compiler/tests/18_port_data_16mux_test.py @@ -19,7 +19,7 @@ class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/18_port_data_2mux_1rw_1r_test.py b/compiler/tests/18_port_data_2mux_1rw_1r_test.py index b116578f..d7479126 100755 --- a/compiler/tests/18_port_data_2mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_2mux_1rw_1r_test.py @@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_2mux_test.py b/compiler/tests/18_port_data_2mux_test.py index 691a2880..d9379f9d 100755 --- a/compiler/tests/18_port_data_2mux_test.py +++ b/compiler/tests/18_port_data_2mux_test.py @@ -19,7 +19,7 @@ class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/18_port_data_4mux_1rw_1r_test.py b/compiler/tests/18_port_data_4mux_1rw_1r_test.py index 7168c264..bcb938bf 100755 --- a/compiler/tests/18_port_data_4mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_4mux_1rw_1r_test.py @@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_4mux_test.py b/compiler/tests/18_port_data_4mux_test.py index db900855..aa8cec14 100755 --- a/compiler/tests/18_port_data_4mux_test.py +++ b/compiler/tests/18_port_data_4mux_test.py @@ -19,7 +19,7 @@ class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/18_port_data_8mux_1rw_1r_test.py b/compiler/tests/18_port_data_8mux_1rw_1r_test.py index d1214441..b45e9280 100755 --- a/compiler/tests/18_port_data_8mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_8mux_1rw_1r_test.py @@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_8mux_test.py b/compiler/tests/18_port_data_8mux_test.py index 7f6fb950..3e3d25cc 100755 --- a/compiler/tests/18_port_data_8mux_test.py +++ b/compiler/tests/18_port_data_8mux_test.py @@ -19,7 +19,7 @@ class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/18_port_data_nomux_1rw_1r_test.py b/compiler/tests/18_port_data_nomux_1rw_1r_test.py index d511ccf0..a1a4240b 100755 --- a/compiler/tests/18_port_data_nomux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_nomux_1rw_1r_test.py @@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_nomux_test.py b/compiler/tests/18_port_data_nomux_test.py index 28e93d20..2ff0d453 100755 --- a/compiler/tests/18_port_data_nomux_test.py +++ b/compiler/tests/18_port_data_nomux_test.py @@ -19,7 +19,7 @@ class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py index 8d6f92bb..efbc00b4 100755 --- a/compiler/tests/18_port_data_spare_cols_test.py +++ b/compiler/tests/18_port_data_spare_cols_test.py @@ -19,7 +19,7 @@ class port_data_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=8, num_words=16, diff --git a/compiler/tests/18_port_data_wmask_1rw_1r_test.py b/compiler/tests/18_port_data_wmask_1rw_1r_test.py index ab1b7d4e..6f256f32 100755 --- a/compiler/tests/18_port_data_wmask_1rw_1r_test.py +++ b/compiler/tests/18_port_data_wmask_1rw_1r_test.py @@ -19,7 +19,7 @@ class port_data_wmask_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index 64f007ba..d243d03f 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -19,7 +19,7 @@ class port_data_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index 9f9f6701..7982968e 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -22,7 +22,7 @@ class multi_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 35f71bf2..94f67aaf 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -22,7 +22,7 @@ class multi_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.bitcell = "pbitcell" # testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent) diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index 3400dd6a..74638380 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -21,7 +21,7 @@ class psingle_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py index c6f117a7..1da7a246 100755 --- a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_16mux_test.py b/compiler/tests/19_single_bank_16mux_test.py index ab3c0ed6..e6033ff6 100755 --- a/compiler/tests/19_single_bank_16mux_test.py +++ b/compiler/tests/19_single_bank_16mux_test.py @@ -21,7 +21,7 @@ class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index ab718f2a..e1cde699 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -21,7 +21,7 @@ class single_bank_1w_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 0 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py index 4244ea69..a67d3ad1 100755 --- a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_2mux_test.py b/compiler/tests/19_single_bank_2mux_test.py index 5062d941..563b76fe 100755 --- a/compiler/tests/19_single_bank_2mux_test.py +++ b/compiler/tests/19_single_bank_2mux_test.py @@ -21,7 +21,7 @@ class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py index caae1997..718ed148 100755 --- a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_4mux_test.py b/compiler/tests/19_single_bank_4mux_test.py index 5e184fc7..54edd6f1 100755 --- a/compiler/tests/19_single_bank_4mux_test.py +++ b/compiler/tests/19_single_bank_4mux_test.py @@ -21,7 +21,7 @@ class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py index aa98ad16..0d063dfb 100755 --- a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_8mux_test.py b/compiler/tests/19_single_bank_8mux_test.py index cc938431..3c5cf73d 100755 --- a/compiler/tests/19_single_bank_8mux_test.py +++ b/compiler/tests/19_single_bank_8mux_test.py @@ -21,7 +21,7 @@ class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/19_single_bank_global_bitline_test.py b/compiler/tests/19_single_bank_global_bitline_test.py index 81d19c5e..7b0ec4ba 100755 --- a/compiler/tests/19_single_bank_global_bitline_test.py +++ b/compiler/tests/19_single_bank_global_bitline_test.py @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py index 388ca7aa..b0c9848b 100755 --- a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_nomux_test.py b/compiler/tests/19_single_bank_nomux_test.py index 6c923898..795c04d4 100755 --- a/compiler/tests/19_single_bank_nomux_test.py +++ b/compiler/tests/19_single_bank_nomux_test.py @@ -21,7 +21,7 @@ class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/19_single_bank_spare_cols_test.py b/compiler/tests/19_single_bank_spare_cols_test.py index 6e416d3d..c779bc04 100755 --- a/compiler/tests/19_single_bank_spare_cols_test.py +++ b/compiler/tests/19_single_bank_spare_cols_test.py @@ -21,7 +21,7 @@ class single_bank_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=4, num_words=16, diff --git a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py index ed0e8ef5..9debdfb8 100755 --- a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py @@ -21,7 +21,7 @@ class single_bank_wmask_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py index f6f18291..20f75924 100755 --- a/compiler/tests/19_single_bank_wmask_test.py +++ b/compiler/tests/19_single_bank_wmask_test.py @@ -21,7 +21,7 @@ class single_bank_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=8, write_size=4, diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index f1dae967..da9cfaec 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -21,7 +21,7 @@ class psram_1bank_2mux_1rw_1w_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py index 9fe51347..c917a63c 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py @@ -21,7 +21,7 @@ class psram_1bank_2mux_1rw_1w_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 51a5518b..f94167dd 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -21,7 +21,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 0 diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 873531cf..803d86a1 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -21,7 +21,7 @@ class psram_1bank_2mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 2c5f7165..5a272da8 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -21,7 +21,7 @@ class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 diff --git a/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py index 209c6a0e..aeede7d6 100755 --- a/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py @@ -21,7 +21,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_16mux_test.py b/compiler/tests/20_sram_1bank_16mux_test.py index 2a013c70..12e19c3b 100755 --- a/compiler/tests/20_sram_1bank_16mux_test.py +++ b/compiler/tests/20_sram_1bank_16mux_test.py @@ -21,7 +21,7 @@ class sram_1bank_8mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py index c0147457..e554e770 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py @@ -21,7 +21,7 @@ class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index 807ebe28..8c94902e 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -21,7 +21,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py index 661efa04..75b5b4be 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py @@ -21,7 +21,7 @@ class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 4056b081..cebb57c8 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -21,7 +21,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_global_test.py b/compiler/tests/20_sram_1bank_2mux_global_test.py index febf3095..1ae8ef5b 100755 --- a/compiler/tests/20_sram_1bank_2mux_global_test.py +++ b/compiler/tests/20_sram_1bank_2mux_global_test.py @@ -21,7 +21,7 @@ class sram_1bank_2mux_global_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.local_array_size = 8 if OPTS.tech_name == "sky130": diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index a2a298c4..808329e9 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -21,7 +21,7 @@ class sram_1bank_2mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py index e7739518..92e1993b 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py @@ -21,7 +21,7 @@ class sram_1bank_2mux_wmask_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py index ae3ba98e..51a4163d 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py @@ -21,7 +21,7 @@ class sram_1bank_2mux_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py index f4386f31..f999ab2d 100755 --- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py +++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py @@ -22,7 +22,7 @@ class sram_1bank_32b_1024_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py index 04c35a54..672429b4 100755 --- a/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py @@ -21,7 +21,7 @@ class sram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 3e60c0db..ecde15bf 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -21,7 +21,7 @@ class sram_1bank_4mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index 524b9a41..3fd26b2c 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -21,7 +21,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index 77674dd5..d5e66036 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -21,7 +21,7 @@ class sram_1bank_8mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py index 48a4b21f..108e5306 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py @@ -21,7 +21,7 @@ class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index c22acadd..3c58404f 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -21,7 +21,7 @@ class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py index 14357b58..4991e640 100755 --- a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py @@ -21,7 +21,7 @@ class sram_1bank_nomux_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index 96ca4413..81472fb2 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -21,7 +21,7 @@ class sram_1bank_nomux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py index 02c15899..cbe2e805 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py @@ -22,7 +22,7 @@ class sram_1bank_nomux_wmask_sparecols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py index bfba1e78..361874a8 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py @@ -21,7 +21,7 @@ class sram_1bank_nomux_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_ring_test.py b/compiler/tests/20_sram_1bank_ring_test.py index e32d1dde..9db0d9f4 100755 --- a/compiler/tests/20_sram_1bank_ring_test.py +++ b/compiler/tests/20_sram_1bank_ring_test.py @@ -22,7 +22,7 @@ class sram_1bank_nomux_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) OPTS.supply_pin_type = "ring" - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index 4a3d6d20..650b0df7 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -22,7 +22,7 @@ class sram_2bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=16, num_words=32, num_banks=2) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index e4a6e6a3..22a43f77 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -31,7 +31,7 @@ class timing_sram_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import delay - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index 9f17f4c6..5a9d1213 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -32,8 +32,8 @@ class model_delay_test(openram_test): reload(characterizer) from openram.characterizer import delay from openram.characterizer import elmore - from openram.modules import sram - from openram.modules import sram_config + from openram import sram + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py index c8b7c0b6..249bea34 100755 --- a/compiler/tests/21_ngspice_delay_extra_rows_test.py +++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py @@ -30,7 +30,7 @@ class timing_sram_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import delay - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=1, num_words=16, num_banks=1, diff --git a/compiler/tests/21_ngspice_delay_global_test.py b/compiler/tests/21_ngspice_delay_global_test.py index fb100c8d..a144be64 100755 --- a/compiler/tests/21_ngspice_delay_global_test.py +++ b/compiler/tests/21_ngspice_delay_global_test.py @@ -31,7 +31,7 @@ class timing_sram_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import delay - from openram.modules import sram_config + from openram import sram_config OPTS.local_array_size = 2 if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index fda9b1b7..9c43e69b 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -30,7 +30,7 @@ class timing_sram_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import delay - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/21_regression_delay_test.py b/compiler/tests/21_regression_delay_test.py index 3c20ca9f..99ce1ac4 100755 --- a/compiler/tests/21_regression_delay_test.py +++ b/compiler/tests/21_regression_delay_test.py @@ -32,8 +32,8 @@ class regression_model_test(openram_test): reload(characterizer) from openram.characterizer import linear_regression from openram.characterizer import neural_network - from openram.modules import sram - from openram.modules import sram_config + from openram import sram + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/21_xyce_delay_test.py b/compiler/tests/21_xyce_delay_test.py index 774d1375..cd6125ab 100755 --- a/compiler/tests/21_xyce_delay_test.py +++ b/compiler/tests/21_xyce_delay_test.py @@ -30,7 +30,7 @@ class timing_sram_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import delay - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index b2ee8778..790358fc 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -38,7 +38,7 @@ class psram_1bank_2mux_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=2, num_words=32, num_banks=1) diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index 047dc9d5..50e2fd2a 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -39,7 +39,7 @@ class psram_1bank_4mux_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=2, num_words=256, num_banks=1) diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index 124305b8..d0a01f24 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -39,7 +39,7 @@ class psram_1bank_8mux_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=4, num_words=256, num_banks=1) diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index 678f0e8a..5334a405 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -39,7 +39,7 @@ class psram_1bank_nomux_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=2, num_words=32, num_banks=1) diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index f5880a6a..e68dab2a 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -31,7 +31,7 @@ class sram_1bank_2mux_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_2mux_global_func_test.py b/compiler/tests/22_sram_1bank_2mux_global_func_test.py index b0c650b8..d97627ca 100755 --- a/compiler/tests/22_sram_1bank_2mux_global_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_global_func_test.py @@ -31,7 +31,7 @@ class sram_1bank_2mux_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config OPTS.local_array_size = 8 if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py index 21266f9d..aa8bcfc2 100755 --- a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py @@ -31,7 +31,7 @@ class sram_1bank_2mux_sparecols_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index 78c34ca7..7c65c2a9 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -31,7 +31,7 @@ class sram_1bank_4mux_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index ac4882a9..bee23ef4 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -34,7 +34,7 @@ class sram_1bank_8mux_func_test(openram_test): if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py index 22cd6290..99133104 100755 --- a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py @@ -35,7 +35,7 @@ class psram_1bank_nomux_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=4, num_words=32, num_banks=1) diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index 8179d4da..5ec95c36 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -31,7 +31,7 @@ class sram_1bank_nomux_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py index d8c5d2f6..765dd571 100755 --- a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py @@ -31,7 +31,7 @@ class sram_1bank_nomux_sparecols_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py index a0d01af2..f690437b 100755 --- a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py +++ b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py @@ -35,7 +35,7 @@ class sram_wmask_1w_1r_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py index d0f75f7b..565c69f8 100755 --- a/compiler/tests/22_sram_wmask_func_test.py +++ b/compiler/tests/22_sram_wmask_func_test.py @@ -31,7 +31,7 @@ class sram_wmask_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/23_lib_sram_linear_regression_test.py b/compiler/tests/23_lib_sram_linear_regression_test.py index 56c0d593..79c021d6 100755 --- a/compiler/tests/23_lib_sram_linear_regression_test.py +++ b/compiler/tests/23_lib_sram_linear_regression_test.py @@ -33,8 +33,8 @@ class lib_sram_linear_regression_test(openram_test): num_spare_cols = 0 from openram.characterizer import lib - from openram.modules import sram - from openram.modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index d79c14ec..71d00a85 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -32,8 +32,8 @@ class lib_model_corners_lib_test(openram_test): num_spare_cols = 0 from openram.characterizer import lib - from openram.modules import sram - from openram.modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 55928c51..183efc29 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -32,8 +32,8 @@ class lib_sram_model_test(openram_test): num_spare_cols = 0 from openram.characterizer import lib - from openram.modules import sram - from openram.modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index 64abb186..b9f1ae19 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -40,8 +40,8 @@ class lib_sram_prune_test(openram_test): num_spare_rows = 0 num_spare_cols = 0 - from openram.modules import sram - from openram.modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index c7a5f564..961dc9e5 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -38,8 +38,8 @@ class lib_test(openram_test): num_spare_rows = 0 num_spare_cols = 0 - from openram.modules import sram - from openram.modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index a134ca62..3d38462f 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -23,8 +23,8 @@ class lef_test(openram_test): openram.init_openram(config_file, is_unit_test=True) OPTS.route_supplies=False OPTS.check_lvsdrc=False - from openram.modules import sram - from openram.modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1) diff --git a/compiler/tests/25_verilog_multibank_test.py b/compiler/tests/25_verilog_multibank_test.py index 552b361a..acd3bc12 100755 --- a/compiler/tests/25_verilog_multibank_test.py +++ b/compiler/tests/25_verilog_multibank_test.py @@ -23,8 +23,8 @@ class multibank_verilog_test(openram_test): OPTS.route_supplies=False OPTS.check_lvsdrc=False OPTS.netlist_only=True - from openram.modules import sram - from openram.modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=2) diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index 023efe56..4d6e4456 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -23,8 +23,8 @@ class verilog_test(openram_test): OPTS.route_supplies=False OPTS.check_lvsdrc=False OPTS.netlist_only=True - from openram.modules import sram - from openram.modules import sram_config + from openram import sram + from openram import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1) diff --git a/compiler/tests/26_sram_pex_test.py b/compiler/tests/26_sram_pex_test.py index 9507e57a..fb6968fb 100755 --- a/compiler/tests/26_sram_pex_test.py +++ b/compiler/tests/26_sram_pex_test.py @@ -30,7 +30,7 @@ class sram_pex_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=4, num_words=32, num_banks=1) diff --git a/compiler/tests/30_openram_back_end_library_test.py b/compiler/tests/30_openram_back_end_library_test.py index 7ed9730b..a56fb427 100755 --- a/compiler/tests/30_openram_back_end_library_test.py +++ b/compiler/tests/30_openram_back_end_library_test.py @@ -49,7 +49,7 @@ class openram_back_end_library_test(openram_test): OPTS.num_threads = 2 # Create an SRAM using the library - from openram.modules import sram + from openram import sram s = sram() s.save() diff --git a/compiler/tests/30_openram_front_end_library_test.py b/compiler/tests/30_openram_front_end_library_test.py index 88d60f72..979b3315 100755 --- a/compiler/tests/30_openram_front_end_library_test.py +++ b/compiler/tests/30_openram_front_end_library_test.py @@ -50,7 +50,7 @@ class openram_front_end_library_test(openram_test): OPTS.num_threads = 2 # Create an SRAM using the library - from openram.modules import sram + from openram import sram s = sram() s.save() diff --git a/compiler/tests/50_riscv_1k_1rw1r_func_test.py b/compiler/tests/50_riscv_1k_1rw1r_func_test.py index c6be45b1..ce82b02c 100755 --- a/compiler/tests/50_riscv_1k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_1k_1rw1r_func_test.py @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=256, diff --git a/compiler/tests/50_riscv_1k_1rw_func_test.py b/compiler/tests/50_riscv_1k_1rw_func_test.py index 8226e1c7..5cd1ae6c 100755 --- a/compiler/tests/50_riscv_1k_1rw_func_test.py +++ b/compiler/tests/50_riscv_1k_1rw_func_test.py @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=256, diff --git a/compiler/tests/50_riscv_1rw1r_func_test.py b/compiler/tests/50_riscv_1rw1r_func_test.py index 0bd41257..9fe291b8 100755 --- a/compiler/tests/50_riscv_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_1rw1r_func_test.py @@ -36,7 +36,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=32, diff --git a/compiler/tests/50_riscv_1rw1r_phys_test.py b/compiler/tests/50_riscv_1rw1r_phys_test.py index a2e1daf4..f0e46162 100755 --- a/compiler/tests/50_riscv_1rw1r_phys_test.py +++ b/compiler/tests/50_riscv_1rw1r_phys_test.py @@ -22,7 +22,7 @@ class riscv_phys_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/50_riscv_1rw_func_test.py b/compiler/tests/50_riscv_1rw_func_test.py index 0cac3a01..5afe61af 100755 --- a/compiler/tests/50_riscv_1rw_func_test.py +++ b/compiler/tests/50_riscv_1rw_func_test.py @@ -44,7 +44,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=64, diff --git a/compiler/tests/50_riscv_1rw_phys_test.py b/compiler/tests/50_riscv_1rw_phys_test.py index 610d23a1..b53225fe 100755 --- a/compiler/tests/50_riscv_1rw_phys_test.py +++ b/compiler/tests/50_riscv_1rw_phys_test.py @@ -22,7 +22,7 @@ class riscv_phys_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) - from openram.modules import sram_config + from openram import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/50_riscv_2k_1rw1r_func_test.py b/compiler/tests/50_riscv_2k_1rw1r_func_test.py index 22daade1..416fd17b 100755 --- a/compiler/tests/50_riscv_2k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_2k_1rw1r_func_test.py @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=512, diff --git a/compiler/tests/50_riscv_2k_1rw_func_test.py b/compiler/tests/50_riscv_2k_1rw_func_test.py index 311aea20..ff26deb7 100755 --- a/compiler/tests/50_riscv_2k_1rw_func_test.py +++ b/compiler/tests/50_riscv_2k_1rw_func_test.py @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=512, diff --git a/compiler/tests/50_riscv_4k_1rw1r_func_test.py b/compiler/tests/50_riscv_4k_1rw1r_func_test.py index fd7b9920..85af4f92 100755 --- a/compiler/tests/50_riscv_4k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_4k_1rw1r_func_test.py @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=1024, diff --git a/compiler/tests/50_riscv_4k_1rw_func_test.py b/compiler/tests/50_riscv_4k_1rw_func_test.py index ba2b1f51..04b8e985 100755 --- a/compiler/tests/50_riscv_4k_1rw_func_test.py +++ b/compiler/tests/50_riscv_4k_1rw_func_test.py @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=1024, diff --git a/compiler/tests/50_riscv_512b_1rw1r_func_test.py b/compiler/tests/50_riscv_512b_1rw1r_func_test.py index e95f92a4..60cc741c 100755 --- a/compiler/tests/50_riscv_512b_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_512b_1rw1r_func_test.py @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=128, diff --git a/compiler/tests/50_riscv_512b_1rw_func_test.py b/compiler/tests/50_riscv_512b_1rw_func_test.py index 70f51b6a..7faefad7 100755 --- a/compiler/tests/50_riscv_512b_1rw_func_test.py +++ b/compiler/tests/50_riscv_512b_1rw_func_test.py @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=128, diff --git a/compiler/tests/50_riscv_8k_1rw1r_func_test.py b/compiler/tests/50_riscv_8k_1rw1r_func_test.py index 0aed27ea..591c96c3 100755 --- a/compiler/tests/50_riscv_8k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_8k_1rw1r_func_test.py @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=2048, diff --git a/compiler/tests/50_riscv_8k_1rw_func_test.py b/compiler/tests/50_riscv_8k_1rw_func_test.py index ead2fd8a..eb5b75f6 100755 --- a/compiler/tests/50_riscv_8k_1rw_func_test.py +++ b/compiler/tests/50_riscv_8k_1rw_func_test.py @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): from openram import characterizer reload(characterizer) from openram.characterizer import functional - from openram.modules import sram_config + from openram import sram_config c = sram_config(word_size=32, write_size=8, num_words=2048, diff --git a/sram_compiler.py b/sram_compiler.py index ced2a430..1dc3812c 100755 --- a/sram_compiler.py +++ b/sram_compiler.py @@ -76,7 +76,7 @@ for path in output_files: debug.print_raw(path) # Create an SRAM (we can also pass sram_config, see documentation/tutorials for details) -from openram.modules import sram +from openram import sram s = sram() # Output the files for the resulting SRAM