mirror of https://github.com/VLSIDA/OpenRAM.git
126 lines
4.9 KiB
Python
Executable File
126 lines
4.9 KiB
Python
Executable File
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import sys, os
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import unittest
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from testutils import *
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import openram
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from openram import debug
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from openram.sram_factory import factory
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from openram import OPTS
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@unittest.skip("SKIPPING 21_ngspice_delay_global_test")
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class timing_sram_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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openram.init_openram(config_file, is_unit_test=True)
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OPTS.spice_name="ngspice"
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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from openram import characterizer
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reload(characterizer)
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from openram.characterizer import delay
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from openram import sram_config
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OPTS.local_array_size = 2
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if OPTS.tech_name == "sky130":
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num_spare_rows = 1
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num_spare_cols = 1
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else:
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num_spare_rows = 0
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num_spare_cols = 0
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c = sram_config(word_size=4,
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num_words=16,
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num_banks=1,
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num_spare_cols=num_spare_cols,
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num_spare_rows=num_spare_rows)
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c.words_per_row=1
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c.recompute_sizes()
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# c = sram_config(word_size=8,
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# num_words=32,
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# num_banks=1)
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# c.words_per_row=2
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# c.recompute_sizes()
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debug.info(1, "Testing timing for global hierarchical array")
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s = factory.create(module_type="sram", sram_config=c)
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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probe_address = "1" * s.s.addr_size
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probe_data = s.s.word_size - 1
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debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data))
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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d = delay(s.s, tempspice, corner)
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from openram import tech
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loads = [tech.spice["dff_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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load_slews = []
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for slew in slews:
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for load in loads:
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load_slews.append((load, slew))
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data, port_data = d.analyze(probe_address, probe_data, load_slews)
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#Combine info about port into all data
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data.update(port_data[0])
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if OPTS.tech_name == "freepdk45":
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golden_data = {'delay_hl': [0.26308339999999997],
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'delay_lh': [0.26308339999999997],
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'disabled_read0_power': [0.1829355],
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'disabled_read1_power': [0.1962055],
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'disabled_write0_power': [0.2130763],
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'disabled_write1_power': [0.2349011],
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'leakage_power': 0.002509793,
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'min_period': 0.977,
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'read0_power': [0.4028693],
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'read1_power': [0.4055884],
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'slew_hl': [0.27116019999999996],
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'slew_lh': [0.27116019999999996],
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'write0_power': [0.44159149999999997],
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'write1_power': [0.3856132]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl': [2.0149939999999997],
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'delay_lh': [2.0149939999999997],
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'disabled_read0_power': [7.751129],
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'disabled_read1_power': [9.025803],
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'disabled_write0_power': [9.546656],
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'disabled_write1_power': [10.2449],
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'leakage_power': 0.004770704,
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'min_period': 7.188,
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'read0_power': [17.68452],
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'read1_power': [18.24353],
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'slew_hl': [1.942796],
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'slew_lh': [1.942796],
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'write0_power': [20.02101],
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'write1_power': [15.389470000000001]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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self.assertTrue(len(data.keys())==len(golden_data.keys()))
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self.assertTrue(self.check_golden_data(data,golden_data,0.25))
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openram.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = openram.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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