mirror of https://github.com/VLSIDA/OpenRAM.git
69 lines
2.5 KiB
Python
Executable File
69 lines
2.5 KiB
Python
Executable File
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import sys, os
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import unittest
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from testutils import *
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import openram
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from openram import debug
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from openram.sram_factory import factory
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from openram import OPTS
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class psram_1bank_2mux_func_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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openram.init_openram(config_file, is_unit_test=True)
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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OPTS.dummy_bitcell="dummy_pbitcell"
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 0
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OPTS.num_w_ports = 1
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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from openram import characterizer
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reload(characterizer)
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from openram.characterizer import functional
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from openram import sram_config
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c = sram_config(word_size=2,
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num_words=32,
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num_banks=1)
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c.words_per_row=2
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c.recompute_sizes()
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debug.info(1, "Functional test for {}rw,{}r,{}w psram with"
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"{} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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s = factory.create(module_type="sram", sram_config=c)
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f = functional(s.s)
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(fail, error) = f.run()
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self.assertTrue(fail, error)
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openram.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = openram.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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