luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

single port fixes

Browse Source
This commit is contained in:
Jesse Cirimelli-Low
2025-09-12 11:25:03 -07:00
parent 4ce6e0538b
commit 5a74605117
9 changed files with 57 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bitcell_array.py
+1 -1
View File
@@ -19,7 +19,7 @@ class bitcell_array(bitcell_base_array):
Creates a rows x cols array of memory cells.
Assumes bit-lines and word lines are connected by abutment.
"""
def __init__(self, rows, cols, column_offset=0, name=""):
def __init__(self, rows, cols, column_offset=0, name="", left_rbl=None, right_rbl=None):
super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
self.add_comment("rows: {0} cols: {1}".format(rows, cols))