diff --git a/Makefile b/Makefile index eb46bebf..6974f1e4 100644 --- a/Makefile +++ b/Makefile @@ -13,7 +13,7 @@ SRAM_LIB_GIT_REPO ?= https://github.com/vlsida/sky130_fd_bd_sram.git # Use this for development #SRAM_LIB_GIT_REPO ?= git@github.com:VLSIDA/sky130_fd_bd_sram.git #SRAM_LIB_GIT_REPO ?= https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git -SRAM_LIB_GIT_COMMIT ?= 9bb620d12ae380dfe38f9a68df809f068f7b2a21 +SRAM_LIB_GIT_COMMIT ?= 32f553d240545574282ac437ff98d2b889bf039f SKY130_PDK ?= $(PDK_ROOT)/sky130A GF180_PDK ?= $(PDK_ROOT)/gf180mcuD diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index db349b8a..6476c71a 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -19,7 +19,7 @@ class bitcell_array(bitcell_base_array): Creates a rows x cols array of memory cells. Assumes bit-lines and word lines are connected by abutment. """ - def __init__(self, rows, cols, column_offset=0, name=""): + def __init__(self, rows, cols, column_offset=0, name="", left_rbl=None, right_rbl=None): super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name) debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) self.add_comment("rows: {0} cols: {1}".format(rows, cols)) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 79704022..12dad632 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -78,7 +78,9 @@ class replica_bitcell_array(bitcell_base_array): self.bitcell_array = factory.create(module_type="bitcell_array", column_offset=len(self.left_rbl), cols=self.column_size, - rows=self.row_size) + rows=self.row_size, + left_rbl=self.left_rbl, + right_rbl=self.right_rbl) # Replica bitlines self.replica_columns = {} diff --git a/compiler/tests/golden/sram_2_16_1_sky130.sp b/compiler/tests/golden/sram_2_16_1_sky130.sp index d68dde96..0f8dc497 100644 --- a/compiler/tests/golden/sram_2_16_1_sky130.sp +++ b/compiler/tests/golden/sram_2_16_1_sky130.sp @@ -833,8 +833,8 @@ Xrca_top_4 X0 ll WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 X1 ul Q_bar_float VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 X2 BL WL ul VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 -*X3 ur WL ur VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 -*X4 lr WL lr VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 +*X3 ur WL ur VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n +*X4 lr WL lr VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n X5 VPWR Q_float lr VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X6 ur Q_bar_float VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X7 VGND Q_float ll VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 @@ -977,8 +977,8 @@ Xrca_19 X0 Q_bar WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 X1 Q Q_bar VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 X2 BL WL Q VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 -*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 -*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 +*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n +*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n X5 VPWR Q Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X6 Q Q_bar VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 @@ -989,8 +989,8 @@ X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 X0 Q_bar WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 X1 Q Q_bar VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 X2 BL WL Q VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 -*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 -*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 +*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n +*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n X5 VPWR Q Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X6 Q Q_bar VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 diff --git a/compiler/tests/sp_files/sram_2_16_1_sky130.sp b/compiler/tests/sp_files/sram_2_16_1_sky130.sp index d68dde96..0f8dc497 100644 --- a/compiler/tests/sp_files/sram_2_16_1_sky130.sp +++ b/compiler/tests/sp_files/sram_2_16_1_sky130.sp @@ -833,8 +833,8 @@ Xrca_top_4 X0 ll WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 X1 ul Q_bar_float VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 X2 BL WL ul VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 -*X3 ur WL ur VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 -*X4 lr WL lr VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 +*X3 ur WL ur VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n +*X4 lr WL lr VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n X5 VPWR Q_float lr VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X6 ur Q_bar_float VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X7 VGND Q_float ll VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 @@ -977,8 +977,8 @@ Xrca_19 X0 Q_bar WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 X1 Q Q_bar VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 X2 BL WL Q VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 -*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 -*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 +*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n +*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n X5 VPWR Q Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X6 Q Q_bar VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 @@ -989,8 +989,8 @@ X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 X0 Q_bar WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 X1 Q Q_bar VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 X2 BL WL Q VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15 -*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 -*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095 +*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n +*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n X5 VPWR Q Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X6 Q Q_bar VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15 X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15 diff --git a/technology/sky130/custom/sky130_bitcell.py b/technology/sky130/custom/sky130_bitcell.py index f99c37c8..f861f707 100644 --- a/technology/sky130/custom/sky130_bitcell.py +++ b/technology/sky130/custom/sky130_bitcell.py @@ -23,6 +23,10 @@ class sky130_bitcell(bitcell_base): cell_name = "sky130_fd_bd_sram__sram_sp_cell_opt1" elif version == "opt1a": cell_name = "sky130_fd_bd_sram__sram_sp_cell_opt1a" + elif version == "opt1_noblcon": + cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1_noblcon" + elif version == "opt1a_noblcon": + cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_noblcon" else: debug.error("Invalid sky130 cell name", -1) diff --git a/technology/sky130/custom/sky130_bitcell_array.py b/technology/sky130/custom/sky130_bitcell_array.py index daf6f899..b6b7a84a 100644 --- a/technology/sky130/custom/sky130_bitcell_array.py +++ b/technology/sky130/custom/sky130_bitcell_array.py @@ -19,14 +19,18 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): Creates a rows x cols array of memory cells. Assumes bit-lines and word lines are connected by abutment. """ - def __init__(self, rows, cols, column_offset=0, name=""): + def __init__(self, rows, cols, column_offset=0, name="",left_rbl=None, right_rbl=None): super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name) - + self.left_rbl = left_rbl + self.right_rbl = right_rbl + def add_modules(self): """ Add the modules used in this design """ # Bitcell for port names only self.cell = factory.create(module_type=OPTS.bitcell, version="opt1") self.cella = factory.create(module_type=OPTS.bitcell, version="opt1a") + #self.cell_noblcon = factory.create(module_type=OPTS.bitcell, version="opt1_noblcon") + #self.cella_noblcon = factory.create(module_type=OPTS.bitcell, version="opt1a_noblcon") self.strap = factory.create(module_type="internal", version="wlstrap") self.strap_p = factory.create(module_type="internal", version="wlstrap_p") self.strapa = factory.create(module_type="internal", version="wlstrapa") @@ -36,6 +40,9 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): """ Create the module instances used in this design """ self.all_inst={} self.cell_inst={} + + #self.cell_noblcon_inst = geometry.instance("cell_noblcon_inst", mod=self.cell_noblcon, is_bitcell=True) + #self.cella_noblcon_inst = geometry.instance("cella_noblcon_inst", mod=self.cella_noblcon, is_bitcell=True) bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True, mirror='XY')] \ + [geometry.instance("01_strap_p", mod=self.strap_p, is_bitcell=False, mirror='MX')]\ @@ -46,11 +53,32 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): + [geometry.instance("11_strap_p", mod=self.strap_p, is_bitcell=False)] \ + [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True)] \ + [geometry.instance("13_strapa", mod=self.strapa, is_bitcell=False)] - + bit_block = [] pattern.append_row_to_block(bit_block, bit_row_opt1) pattern.append_row_to_block(bit_block, bit_row_opt1a) + for row in bit_block: row = pattern.rotate_list(row, self.column_offset * 2) + self.pattern = pattern(self, "bitcell_array", bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="bit_r{0}_c{1}") + self.pattern.connect_array() + + # for i in range(len(self.insts)): + # if self.left_rbl: + # if "r{}".format(self.row_size-1) in self.insts[i].name: + # if self.insts[i].mod == self.cell: + # self.insts[i].mod = self.cell_noblcon_inst.mod + # self.insts[i].gds = self.cell_noblcon_inst.gds + # elif self.insts[i].mod == self.cella: + # self.insts[i].mod = self.cella_noblcon_inst.mod + # self.insts[i].gds = self.cella_noblcon_inst.gds + # if self.right_rbl: + # if "r{}".format("0") in self.insts[i].name: + # if self.insts[i].mod == self.cell: + # self.insts[i].mod = self.cell_noblcon_inst.mod + # self.insts[i].gds = self.cell_noblcon_inst.gds + # elif self.insts[i].mod == self.cella: + # self.insts[i].mod = self.cella_noblcon_inst.mod + # self.insts[i].gds = self.cella_noblcon_inst.gds diff --git a/technology/sky130/custom/sky130_dummy_array.py b/technology/sky130/custom/sky130_dummy_array.py index a95a0b4e..798daaea 100644 --- a/technology/sky130/custom/sky130_dummy_array.py +++ b/technology/sky130/custom/sky130_dummy_array.py @@ -50,9 +50,9 @@ class sky130_dummy_array(dummy_array, sky130_bitcell_base_array): bit_block = [] if(self.row_offset % 2 == 0): - next_row = 0 - else: next_row = 1 + else: + next_row = 0 for i in range(self.row_size): if next_row == 0: diff --git a/technology/sky130/tech/tech.py b/technology/sky130/tech/tech.py index fe2be437..40e12903 100755 --- a/technology/sky130/tech/tech.py +++ b/technology/sky130/tech/tech.py @@ -814,7 +814,9 @@ flatglob = ["*_?mos_m*", blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell", "sky130_fd_bd_sram__openram_dp_cell_dummy", "sky130_fd_bd_sram__openram_dp_cell_replica", - + + "sky130_fd_bd_sram__openram_sp_cell_opt1_noblcon", + "sky130_fd_bd_sram__openram_sp_cell_opt1a_noblcon", "sky130_fd_bd_sram__openram_sp_colend_replica", "sky130_fd_bd_sram__openram_sp_colenda_replica", "sky130_fd_bd_sram__sram_sp_cell_opt1a",