luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-22 06:07:31 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fix regexes for cells without well taps

Browse Source
This commit is contained in:
mrg
2021-11-22 11:33:27 -08:00
parent acc9b2d223
commit 2e846cb22f
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
technology/freepdk45/tech/freepdk45.lylvs
+1 -1
View File
@@ -214,7 +214,7 @@ end
#connect_global(nwell, "NWELL")
#connect_global(bulk, "BULK")
for pat in %w(pnand* and?_dec port_address* replica_bitcell_array)
for pat in %w(pinv* pnor* pnand* and?_dec* port_address* replica_bitcell_array*)
connect_explicit(pat, [ "NWELL", "vdd" ])
connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
end
technology/scn4m_subm/tech/scn4m_subm.lylvs
+1 -1
View File
@@ -164,7 +164,7 @@ connect_global(pwell, "PWELL")
connect_global(nwell, "NWELL")
#connect_global(bulk, "BULK")
for pat in %w(pnand* and?_dec port_address* replica_bitcell_array)
for pat in %w(pinv* pnor* pnand* and?_dec* port_address* replica_bitcell_array*)
connect_explicit(pat, [ "NWELL", "vdd" ])
connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
end