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Change ratio of delay line and RBL size. Need to tune it better automatically.

This commit is contained in:
Matt Guthaus 2018-02-14 16:50:08 -08:00
parent 9559421ca8
commit 2e3e95efda
1 changed files with 2 additions and 2 deletions
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4
compiler/modules/control_logic.py
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@ -69,8 +69,8 @@ class control_logic(design.design):
c = reload(__import__(OPTS.replica_bitline)) c = reload(__import__(OPTS.replica_bitline))
replica_bitline = getattr(c, OPTS.replica_bitline) replica_bitline = getattr(c, OPTS.replica_bitline)
# FIXME: These should be tuned according to the size! # FIXME: These should be tuned according to the size!
FO4_stages = 8 FO4_stages = 6
bitcell_loads = int(math.ceil(self.num_rows / 10.0)) bitcell_loads = int(math.ceil(self.num_rows / 5.0))
self.replica_bitline = replica_bitline(FO4_stages, bitcell_loads) self.replica_bitline = replica_bitline(FO4_stages, bitcell_loads)
self.add_mod(self.replica_bitline) self.add_mod(self.replica_bitline)