From 2e3e95efdacb3f1c4b7c884591c57a87f640fdb1 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 14 Feb 2018 16:50:08 -0800 Subject: [PATCH] Change ratio of delay line and RBL size. Need to tune it better automatically. --- compiler/modules/control_logic.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index a3de587c..861ea6be 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -69,8 +69,8 @@ class control_logic(design.design): c = reload(__import__(OPTS.replica_bitline)) replica_bitline = getattr(c, OPTS.replica_bitline) # FIXME: These should be tuned according to the size! - FO4_stages = 8 - bitcell_loads = int(math.ceil(self.num_rows / 10.0)) + FO4_stages = 6 + bitcell_loads = int(math.ceil(self.num_rows / 5.0)) self.replica_bitline = replica_bitline(FO4_stages, bitcell_loads) self.add_mod(self.replica_bitline)