diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index a3de587c..861ea6be 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -69,8 +69,8 @@ class control_logic(design.design):
         c = reload(__import__(OPTS.replica_bitline))
         replica_bitline = getattr(c, OPTS.replica_bitline)
         # FIXME: These should be tuned according to the size!
-        FO4_stages = 8
-        bitcell_loads = int(math.ceil(self.num_rows / 10.0))
+        FO4_stages = 6
+        bitcell_loads = int(math.ceil(self.num_rows / 5.0))
         self.replica_bitline = replica_bitline(FO4_stages, bitcell_loads)
         self.add_mod(self.replica_bitline)