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https://github.com/VLSIDA/OpenRAM.git
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SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh.
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@@ -26,7 +26,7 @@ class library_drc_test(unittest.TestCase):
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drc_errors += 1
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debug.error("Missing GDS file: {}".format(gds_name))
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drc_errors += verify.run_drc(name, gds_name)
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self.assertEqual(drc_errors, 0)
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# fails if there are any DRC errors on any cells
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self.assertEqual(drc_errors, 0)
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globals.end_openram()
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@@ -28,7 +28,7 @@ class library_lvs_test(unittest.TestCase):
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lvs_errors += 1
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debug.error("Missing SPICE file {}".format(gds_name))
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lvs_errors += verify.run_lvs(f, gds_name, sp_name)
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self.assertEqual(lvs_errors, 0)
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# fail if the error count is not zero
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self.assertEqual(lvs_errors, 0)
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globals.end_openram()
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