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https://github.com/VLSIDA/OpenRAM.git
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fix indentation errors, typos, and missing iterator
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@@ -368,6 +368,7 @@ class control_logic_delay(design.design):
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self.route_sen()
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self.route_delay()
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self.route_pen()
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self.route_glitches()
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self.route_clk_buf()
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self.route_gated_clk_bar()
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self.route_gated_clk_buf()
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@@ -391,10 +392,10 @@ class control_logic_delay(design.design):
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self.delay_inst.place(offset, mirror="MX")
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def route_delay(self):
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delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"],
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delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], \
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["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"])
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slef.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus)
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self.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus)
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# glitch{1-3} are internal timing signals based on different in/out
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# points on the delay chain for adjustable start time and duration
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@@ -646,7 +647,7 @@ class control_logic_delay(design.design):
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def place_wen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row)
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x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row)
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x_offset = self.place_util(self.w_en_gate_inst, x_offset, row)
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self.row_end_inst.append(self.w_en_gate_inst)
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