From 1e1ec54275922b6c8f15f0dc5bbbe130500f91b7 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Sat, 25 Jun 2022 15:14:46 -0700 Subject: [PATCH] fix indentation errors, typos, and missing iterator --- compiler/modules/control_logic_delay.py | 7 ++++--- compiler/modules/multi_delay_chain.py | 7 ++++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index df02f6ff..b7ab686c 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -368,6 +368,7 @@ class control_logic_delay(design.design): self.route_sen() self.route_delay() self.route_pen() + self.route_glitches() self.route_clk_buf() self.route_gated_clk_bar() self.route_gated_clk_buf() @@ -391,10 +392,10 @@ class control_logic_delay(design.design): self.delay_inst.place(offset, mirror="MX") def route_delay(self): - delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], + delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], \ ["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"]) - slef.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus) + self.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus) # glitch{1-3} are internal timing signals based on different in/out # points on the delay chain for adjustable start time and duration @@ -646,7 +647,7 @@ class control_logic_delay(design.design): def place_wen_row(self, row): x_offset = self.control_x_offset - x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row) + x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row) x_offset = self.place_util(self.w_en_gate_inst, x_offset, row) self.row_end_inst.append(self.w_en_gate_inst) diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py index d59a14a4..4c06d91e 100644 --- a/compiler/modules/multi_delay_chain.py +++ b/compiler/modules/multi_delay_chain.py @@ -217,10 +217,10 @@ class multi_delay_chain(design.design): layer="m2", offset=mid_loc) - delay_number = 1 - for pin_number in pinout_list: + delay_number = 1 + for pin_number in self.pinout_list: # output is A pin of last load/fanout inverter - output_driver_inst = self.driver_inst_list[pin_number] + output_driver_inst = self.driver_inst_list[pin_number - 1] a_pin = self.load_inst_map[output_driver_inst][-1].get_pin("A") self.add_via_stack_center(from_layer=a_pin.layer, to_layer="m1", @@ -228,3 +228,4 @@ class multi_delay_chain(design.design): self.add_layout_pin_rect_center(text="delay{}".format(str(delay_number)), layer="m1", offset=a_pin.center()) + delay_number += 1