luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

Clean up multiport test options to be consistent.

Browse Source
This commit is contained in:
mrg
2019-07-12 10:39:55 -07:00
parent aa552f8e96
commit 17d144b5b5
14 changed files with 37 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/control_logic.py
+1 -2
View File
@@ -365,9 +365,8 @@ class control_logic(design.design):
self.create_wlen_row()
if (self.port_type == "rw") or (self.port_type == "w"):
self.create_wen_row()
if self.port_type == "rw":
self.create_rbl_row()
if (self.port_type == "rw") or (self.port_type == "r"):
self.create_rbl_row()
self.create_pen_row()
self.create_sen_row()
self.create_delay()