From 17d144b5b547ba2d8ca52bb07d3bef4c1762eb18 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 12 Jul 2019 10:39:55 -0700 Subject: [PATCH] Clean up multiport test options to be consistent. --- compiler/modules/control_logic.py | 3 +-- compiler/tests/05_bitcell_1rw_1r_array_test.py | 9 ++++++--- compiler/tests/05_replica_bitcell_1rw_1r_array_test.py | 7 +++++-- compiler/tests/19_single_bank_1rw_1r_test.py | 9 ++++++--- compiler/tests/19_single_bank_1w_1r_test.py | 9 ++++++--- compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py | 3 ++- compiler/tests/20_psram_1bank_2mux_1w_1r_test.py | 3 ++- compiler/tests/20_psram_1bank_2mux_test.py | 1 + compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py | 3 ++- compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py | 1 + compiler/tests/20_sram_1bank_2mux_1w_1r_test.py | 3 ++- compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py | 1 + compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py | 1 + compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py | 1 + 14 files changed, 37 insertions(+), 17 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index f67507b9..c795888a 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -365,9 +365,8 @@ class control_logic(design.design): self.create_wlen_row() if (self.port_type == "rw") or (self.port_type == "w"): self.create_wen_row() - if self.port_type == "rw": - self.create_rbl_row() if (self.port_type == "rw") or (self.port_type == "r"): + self.create_rbl_row() self.create_pen_row() self.create_sen_row() self.create_delay() diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 78d8d646..972fb8e6 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -21,13 +21,16 @@ class bitcell_1rw_1r_array_test(openram_test): def runTest(self): - debug.info(2, "Testing 4x4 array for cell_1rw_1r") + globals.init_openram("config_{0}".format(OPTS.tech_name)) + + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.replica_bitcell = "replica_bitcell_1rw_1r" + OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.init_openram("config_{0}".format(OPTS.tech_name)) - + debug.info(2, "Testing 4x4 array for cell_1rw_1r") a = factory.create(module_type="bitcell_array", cols=4, rows=4) self.local_check(a) diff --git a/compiler/tests/05_replica_bitcell_1rw_1r_array_test.py b/compiler/tests/05_replica_bitcell_1rw_1r_array_test.py index 6a7c6aaf..ddf6be60 100755 --- a/compiler/tests/05_replica_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_replica_bitcell_1rw_1r_array_test.py @@ -16,12 +16,15 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): + globals.init_openram("config_{0}".format(OPTS.tech_name)) + + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.replica_bitcell = "replica_bitcell_1rw_1r" + OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.init_openram("config_{0}".format(OPTS.tech_name)) - debug.info(2, "Testing 4x4 array for cell_1rw_1r") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1) self.local_check(a) diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index 690c621c..ab5ce041 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -18,13 +18,16 @@ import debug class single_bank_1rw_1r_test(openram_test): def runTest(self): + globals.init_openram("config_{0}".format(OPTS.tech_name)) + from sram_config import sram_config + + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.replica_bitcell = "replica_bitcell_1rw_1r" + OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.init_openram("config_{0}".format(OPTS.tech_name)) - - from sram_config import sram_config c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index 7c8ad56e..81d4c8e6 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -18,13 +18,16 @@ import debug class single_bank_1w_1r_test(openram_test): def runTest(self): + globals.init_openram("config_{0}".format(OPTS.tech_name)) + from sram_config import sram_config + + OPTS.bitcell = "bitcell_1w_1r" + OPTS.replica_bitcell = "replica_bitcell_1w_1r" + OPTS.dummy_bitcell="dummy_bitcell_1w_1r" OPTS.num_rw_ports = 0 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 - globals.init_openram("config_{0}".format(OPTS.tech_name)) - - from sram_config import sram_config c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index cd7086b6..fdeae56f 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -21,9 +21,10 @@ class psram_1bank_2mux_1rw_1w_test(openram_test): def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config + OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" - + OPTS.dummy_bitcell="dummy_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 1 OPTS.num_r_ports = 0 diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 8b716d43..a5c01d8f 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -21,9 +21,10 @@ class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config + OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" - + OPTS.dummy_bitcell="dummy_pbitcell" OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 5f0cba17..64fa72ca 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -23,6 +23,7 @@ class psram_1bank_2mux_test(openram_test): from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" + OPTS.dummy_bitcell="dummy_pbitcell" # testing layout of sram using pbitcell with 1 RW port (a 6T-cell equivalent) OPTS.num_rw_ports = 1 diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index d674c04e..7779b794 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -20,9 +20,10 @@ class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config + OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" - + OPTS.dummy_bitcell="dummy_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index acaf5844..60192759 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -23,6 +23,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test): OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" + OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 50af484f..2e1e848f 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -21,9 +21,10 @@ class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config + OPTS.bitcell = "bitcell_1w_1r" OPTS.replica_bitcell="replica_bitcell_1w_1r" - + OPTS.dummy_bitcell="dummy_bitcell_1w_1r" OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index 1cd89037..48a42106 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -23,6 +23,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test): OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" + OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index 570cf092..f6bccc13 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -23,6 +23,7 @@ class sram_1bank_nomux_1rw_1r_test(openram_test): OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" + OPTS.dummy_bitcell = "dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py index e733fce3..fb85f5bf 100755 --- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py @@ -25,6 +25,7 @@ class psram_1bank_nomux_func_test(openram_test): OPTS.trim_netlist = False OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" + OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 1