2017-08-24 00:02:15 +02:00
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import debug
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import design
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from tech import drc
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from pinv import pinv
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from contact import contact
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from vector import vector
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from globals import OPTS
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class delay_chain(design.design):
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"""
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2018-02-14 00:54:50 +01:00
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Generate a delay chain with the given number of stages and fanout.
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2018-07-19 19:51:20 +02:00
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Input is a list contains the electrical effort (fanout) of each stage.
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Usually, this will be constant, but it could have varied fanout.
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2017-08-24 00:02:15 +02:00
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"""
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2018-09-27 04:10:24 +02:00
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unique_id = 1
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2017-08-24 00:02:15 +02:00
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def __init__(self, fanout_list, name="delay_chain"):
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"""init function"""
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2018-09-27 04:10:24 +02:00
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name = name+"_{}".format(delay_chain.unique_id)
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delay_chain.unique_id += 1
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2017-08-24 00:02:15 +02:00
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design.design.__init__(self, name)
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2018-07-19 19:51:20 +02:00
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# Two fanouts are needed so that we can route the vdd/gnd connections
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2018-02-16 20:51:01 +01:00
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for f in fanout_list:
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2018-07-19 19:51:20 +02:00
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debug.check(f>=2,"Must have >=2 fanouts for each stage.")
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2018-02-16 20:51:01 +01:00
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2017-08-24 00:02:15 +02:00
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# number of inverters including any fanout loads.
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self.fanout_list = fanout_list
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2018-08-28 01:42:48 +02:00
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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2017-08-24 00:02:15 +02:00
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2018-08-28 01:42:48 +02:00
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def create_netlist(self):
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self.add_modules()
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2018-08-28 19:24:09 +02:00
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self.add_pins()
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2018-08-28 01:42:48 +02:00
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self.create_inverters()
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def create_layout(self):
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# Each stage is a a row
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self.height = len(self.fanout_list)*self.inv.height
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# The width is determined by the largest fanout plus the driver
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self.width = (max(self.fanout_list)+1) * self.inv.width
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self.place_inverters()
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2018-03-12 21:14:53 +01:00
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self.route_inverters()
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2017-08-24 00:02:15 +02:00
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self.add_layout_pins()
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self.DRC_LVS()
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def add_pins(self):
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""" Add the pins of the delay chain"""
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self.add_pin("in")
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self.add_pin("out")
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self.add_pin("vdd")
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self.add_pin("gnd")
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2018-08-28 01:42:48 +02:00
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def add_modules(self):
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2017-08-24 00:02:15 +02:00
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self.inv = pinv(route_output=False)
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self.add_mod(self.inv)
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2018-08-28 01:42:48 +02:00
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def create_inverters(self):
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""" Create the inverters and connect them based on the stage list """
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2018-03-12 21:14:53 +01:00
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self.driver_inst_list = []
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self.rightest_load_inst = {}
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self.load_inst_map = {}
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for stage_num,fanout_size in zip(range(len(self.fanout_list)),self.fanout_list):
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# Add the inverter
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cur_driver=self.add_inst(name="dinv{}".format(stage_num),
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2018-08-28 01:42:48 +02:00
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mod=self.inv)
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2017-08-24 00:02:15 +02:00
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# keep track of the inverter instances so we can use them to get the pins
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2018-03-12 21:14:53 +01:00
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self.driver_inst_list.append(cur_driver)
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2017-08-24 00:02:15 +02:00
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2018-03-12 21:14:53 +01:00
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# Hook up the driver
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if stage_num+1==len(self.fanout_list):
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stageout_name = "out"
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2017-08-24 00:02:15 +02:00
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else:
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2018-03-12 21:14:53 +01:00
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stageout_name = "dout_{}".format(stage_num+1)
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if stage_num == 0:
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stagein_name = "in"
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2017-08-24 00:02:15 +02:00
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else:
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2018-03-12 21:14:53 +01:00
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stagein_name = "dout_{}".format(stage_num)
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self.connect_inst([stagein_name, stageout_name, "vdd", "gnd"])
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# Now add the dummy loads to the right
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self.load_inst_map[cur_driver]=[]
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for i in range(fanout_size):
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cur_load=self.add_inst(name="dload_{0}_{1}".format(stage_num,i),
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2018-08-28 01:42:48 +02:00
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mod=self.inv)
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2018-03-12 21:14:53 +01:00
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# Fanout stage is always driven by driver and output is disconnected
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disconnect_name = "n_{0}_{1}".format(stage_num,i)
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self.connect_inst([stageout_name, disconnect_name, "vdd", "gnd"])
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# Keep track of all the loads to connect their inputs as a load
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self.load_inst_map[cur_driver].append(cur_load)
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else:
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# Keep track of the last one so we can add the the wire later
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self.rightest_load_inst[cur_driver]=cur_load
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2018-08-28 01:42:48 +02:00
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def place_inverters(self):
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""" Place the inverters and connect them based on the stage list """
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for stage_num,fanout_size in zip(range(len(self.fanout_list)),self.fanout_list):
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if stage_num % 2:
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inv_mirror = "MX"
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inv_offset = vector(0, (stage_num+1)* self.inv.height)
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else:
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inv_mirror = "R0"
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inv_offset = vector(0, stage_num * self.inv.height)
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# Add the inverter
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2018-08-28 02:25:39 +02:00
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cur_driver=self.driver_inst_list[stage_num]
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cur_driver.place(offset=inv_offset,
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mirror=inv_mirror)
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2018-08-28 01:42:48 +02:00
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# Now add the dummy loads to the right
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2018-08-28 02:25:39 +02:00
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load_list = self.load_inst_map[cur_driver]
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2018-08-28 01:42:48 +02:00
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for i in range(fanout_size):
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inv_offset += vector(self.inv.width,0)
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2018-08-28 02:25:39 +02:00
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load_list[i].place(offset=inv_offset,
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mirror=inv_mirror)
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2018-08-28 01:42:48 +02:00
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2018-03-12 21:14:53 +01:00
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2017-12-12 23:53:19 +01:00
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def add_route(self, pin1, pin2):
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""" This guarantees that we route from the top to bottom row correctly. """
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pin1_pos = pin1.center()
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pin2_pos = pin2.center()
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if pin1_pos.y == pin2_pos.y:
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self.add_path("metal2", [pin1_pos, pin2_pos])
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else:
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mid_point = vector(pin2_pos.x, 0.5*(pin1_pos.y+pin2_pos.y))
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# Written this way to guarantee it goes right first if we are switching rows
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self.add_path("metal2", [pin1_pos, vector(pin1_pos.x,mid_point.y), mid_point, vector(mid_point.x,pin2_pos.y), pin2_pos])
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2018-03-12 21:14:53 +01:00
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def route_inverters(self):
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2017-08-24 00:02:15 +02:00
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""" Add metal routing for each of the fanout stages """
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2018-03-12 21:14:53 +01:00
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for i in range(len(self.driver_inst_list)):
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inv = self.driver_inst_list[i]
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for load in self.load_inst_map[inv]:
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# Drop a via on each A pin
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a_pin = load.get_pin("A")
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self.add_via_center(layers=("metal1","via1","metal2"),
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2018-03-14 18:53:20 +01:00
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offset=a_pin.center())
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2018-03-12 21:14:53 +01:00
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self.add_via_center(layers=("metal2","via2","metal3"),
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2018-03-14 18:53:20 +01:00
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offset=a_pin.center())
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2018-03-12 21:14:53 +01:00
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# Route an M3 horizontal wire to the furthest
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z_pin = inv.get_pin("Z")
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a_pin = inv.get_pin("A")
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a_max = self.rightest_load_inst[inv].get_pin("A")
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self.add_via_center(layers=("metal1","via1","metal2"),
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2018-03-14 18:53:20 +01:00
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offset=a_pin.center())
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2018-03-12 21:14:53 +01:00
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self.add_via_center(layers=("metal1","via1","metal2"),
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2018-03-14 18:53:20 +01:00
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offset=z_pin.center())
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2018-03-12 21:14:53 +01:00
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self.add_via_center(layers=("metal2","via2","metal3"),
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2018-03-14 18:53:20 +01:00
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offset=z_pin.center())
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2018-03-12 21:14:53 +01:00
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self.add_path("metal3",[z_pin.center(), a_max.center()])
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2017-08-24 00:02:15 +02:00
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2018-03-12 21:14:53 +01:00
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# Route Z to the A of the next stage
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if i+1 < len(self.driver_inst_list):
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z_pin = inv.get_pin("Z")
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next_inv = self.driver_inst_list[i+1]
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next_a_pin = next_inv.get_pin("A")
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y_mid = (z_pin.cy() + next_a_pin.cy())/2
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mid1_point = vector(z_pin.cx(), y_mid)
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mid2_point = vector(next_a_pin.cx(), y_mid)
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self.add_path("metal2",[z_pin.center(), mid1_point, mid2_point, next_a_pin.center()])
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2017-12-12 23:53:19 +01:00
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2018-03-12 21:14:53 +01:00
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2017-08-24 00:02:15 +02:00
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def add_layout_pins(self):
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""" Add vdd and gnd rails and the input/output. Connect the gnd rails internally on
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the top end with no input/output to obstruct. """
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2018-03-12 21:14:53 +01:00
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2018-07-19 19:23:08 +02:00
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# Add power and ground to all the cells except:
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# the fanout driver, the right-most load
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# The routing to connect the loads is over the first and last cells
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2018-07-19 19:37:47 +02:00
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# We have an even number of drivers and must only do every other
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# supply rail
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for i in range(0,len(self.driver_inst_list),2):
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inv = self.driver_inst_list[i]
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for load in self.load_inst_map[inv]:
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if load==self.rightest_load_inst[inv]:
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continue
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for pin_name in ["vdd", "gnd"]:
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2018-07-19 19:23:08 +02:00
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pin = load.get_pin(pin_name)
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2018-08-30 02:21:53 +02:00
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self.add_power_pin(pin_name, pin.rc())
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2018-07-19 19:37:47 +02:00
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else:
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# We have an even number of rows, so need to get the last gnd rail
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inv = self.driver_inst_list[-1]
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for load in self.load_inst_map[inv]:
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if load==self.rightest_load_inst[inv]:
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continue
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pin_name = "gnd"
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pin = load.get_pin(pin_name)
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2018-08-30 02:21:53 +02:00
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self.add_power_pin(pin_name, pin.rc())
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2018-07-19 19:37:47 +02:00
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2018-03-12 21:14:53 +01:00
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2017-08-24 00:02:15 +02:00
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# input is A pin of first inverter
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2018-03-12 21:14:53 +01:00
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a_pin = self.driver_inst_list[0].get_pin("A")
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self.add_via_center(layers=("metal1","via1","metal2"),
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2018-03-14 18:53:20 +01:00
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offset=a_pin.center())
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2017-08-24 00:02:15 +02:00
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self.add_layout_pin(text="in",
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2018-03-12 21:14:53 +01:00
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layer="metal2",
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offset=a_pin.ll().scale(1,0),
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height=a_pin.cy())
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2017-08-24 00:02:15 +02:00
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2018-03-12 21:14:53 +01:00
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# output is A pin of last load inverter
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last_driver_inst = self.driver_inst_list[-1]
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a_pin = self.rightest_load_inst[last_driver_inst].get_pin("A")
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self.add_via_center(layers=("metal1","via1","metal2"),
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2018-03-14 18:53:20 +01:00
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offset=a_pin.center())
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2018-03-12 21:14:53 +01:00
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mid_point = vector(a_pin.cx()+3*self.m2_width,a_pin.cy())
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self.add_path("metal2",[a_pin.center(), mid_point, mid_point.scale(1,0)])
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2018-03-21 21:20:48 +01:00
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self.add_layout_pin_segment_center(text="out",
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2018-03-14 18:53:20 +01:00
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layer="metal2",
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start=mid_point,
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end=mid_point.scale(1,0))
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2017-08-24 00:02:15 +02:00
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