luke
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  • Joined on 2024-06-02
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xschem
C 0 0 0
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2026-09-08 19:24:19 +02:00
verilator
SystemVerilog 0 0 0
Verilator open-source SystemVerilog simulator and lint system
rtl verilog cpp compilers verilog-simulator verilator systemc system-verilog
Updated 2026-09-08 17:08:34 +02:00
yosys
C++ 0 0 0
Yosys Open SYnthesis Suite
Updated 2026-09-08 12:31:12 +02:00
prjxray
Python 0 0 0
Documenting the Xilinx 7-series bit-stream format.
Updated 2026-09-08 10:13:39 +02:00
cxxopt
C++ 0 0 0
Lightweight C++ command line option parser
positional-arguments option-parser c-plus-plus
Updated 2026-09-08 09:57:33 +02:00
sbt
Scala 0 0 0
sbt, the interactive build tool
scala zinc sbt build-tool
Updated 2026-09-08 04:46:36 +02:00
iverilog
C++ 0 0 0
Icarus Verilog
Updated 2026-09-08 02:52:08 +02:00
prjxray-db
Shell 0 0 0
Project X-Ray Database: XC7 Series
Updated 2026-09-08 02:18:01 +02:00
ngspice
C 0 0 0
Updated 2026-09-07 22:36:36 +02:00
nextpnr
C++ 0 0 0
nextpnr portable FPGA place and route tool
Updated 2026-09-06 14:02:16 +02:00
klayout
C++ 0 0 0
KLayout Main Sources
qt klayout gds2 eda
Updated 2026-09-05 01:02:40 +02:00
OpenSTA
C++ 0 0 0
OpenSTA engine
Updated 2026-09-04 12:39:54 +02:00
openFPGALoader
C++ 0 0 0
Universal utility for programming FPGA
fpga xilinx bitstream trenz-gowin-littlebee arty lattice intel gowin cyclone
Updated 2026-09-04 12:13:36 +02:00
magic
C 0 0 0
Magic VLSI Layout Tool
Updated 2026-09-01 20:59:07 +02:00
taxi
SystemVerilog 0 0 0
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
Updated 2026-08-28 22:34:16 +02:00