luke
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  • Joined on 2024-06-02
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manta
Python 0 0
A configurable and approachable tool for FPGA debugging and rapid prototyping.
fpga verilog icestorm icestick debug xilinx
Updated 2026-03-29 05:44:03 +02:00
sv2v
Haskell 0 0
SystemVerilog to Verilog conversion
verilog yosys systemverilog conversion
Updated 2026-03-27 23:46:29 +01:00
prjxray
Python 0 0
Documenting the Xilinx 7-series bit-stream format.
Updated 2026-03-24 17:02:55 +01:00
IHP-AnalogAcademy
Jupyter Notebook 0 0
Updated 2026-02-17 16:08:52 +01:00
UberDDR3
Verilog 0 0
Opensource DDR3 Controller
fpga verilog controller phy memory-controller ddr3-phy ddr3-controller ddr3
Updated 2026-01-18 05:25:34 +01:00
ndk-fpga
0 0
Updated 2025-06-19 20:36:45 +02:00
icestorm
Python 0 0
Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
Updated 2025-06-03 14:40:39 +02:00