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Add MachXO2 to the table, plus symbol legend.

William D. Jones 2021-11-06 15:48:53 -04:00
parent f8af61e805
commit 4bdab1833c
1 changed files with 27 additions and 20 deletions
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47
FPGA-family-feature-matrix.md

@ -4,23 +4,30 @@ There is a growing number of FPGA families that have support in the open source
The table on this page aims to keep track of which FPGA primitives are supported by which project.
| FPGA Family | Gowin LittleBee |
|----------------|-----------------|
| Project | Apicula |
| Logic Slice | ✔️ |
| ├ LUTRAM | ❌ |
| └ ALU | ✔️ |
| IO buffer | ✔️ |
| ├ IO standards | ✔️ |
| └ DDR/SERDES | ❌ |
| Block RAM | ❌ |
| DSP | ❌ |
| PLL | ❌ |
| Routing | ✔️ |
| ├ Local | ✔️ |
| ├ Global | ✔️ |
| └ Long wires | ❌ |
| Timing | ✔️ |
| ├ Logic | ✔️ |
| ├ Routing | ✔️ |
| └ IO buffer | ✔️ |
| FPGA Family | Gowin LittleBee | MachXO2 |
|----------------|-----------------|-----------------|
| Project | Apicula |Facade/Trellis |
| Logic Slice | ✔️ |✔️ |
| ├ LUTRAM | ❌ |❌ |
| └ ALU | ✔️ |❌ |
| IO buffer | ✔️ |✔️ |
| ├ IO standards | ✔️ |⚠️ |
| └ DDR/SERDES | ❌ |❌ |
| Block RAM | ❌ |❌ |
| DSP | ❌ |❌ |
| PLL | ❌ |❌ |
| Routing | ✔️ |✔️ |
| ├ Local | ✔️ |✔️ |
| ├ Global | ✔️ |🚧 |
| └ Long wires | ❌ |❌ (N/A) |
| Timing | ✔️ |❌ |
| ├ Logic | ✔️ |❌ |
| ├ Routing | ✔️ |❌ |
| └ IO buffer | ✔️ |❌ |
| symbol | meaning |
|--------|--------------------------------------|
| ✔️ | complete, reliable |
| ⚠️ | nominally complete, not well-tested |
| 🚧 | incomplete |
| ❌ | unimplemented |