diff --git a/FPGA-family-feature-matrix.md b/FPGA-family-feature-matrix.md index 2e16e62..979749e 100644 --- a/FPGA-family-feature-matrix.md +++ b/FPGA-family-feature-matrix.md @@ -4,23 +4,30 @@ There is a growing number of FPGA families that have support in the open source The table on this page aims to keep track of which FPGA primitives are supported by which project. -| FPGA Family | Gowin LittleBee | -|----------------|-----------------| -| Project | Apicula | -| Logic Slice | ✔️ | -| ├ LUTRAM | ❌ | -| └ ALU | ✔️ | -| IO buffer | ✔️ | -| ├ IO standards | ✔️ | -| └ DDR/SERDES | ❌ | -| Block RAM | ❌ | -| DSP | ❌ | -| PLL | ❌ | -| Routing | ✔️ | -| ├ Local | ✔️ | -| ├ Global | ✔️ | -| └ Long wires | ❌ | -| Timing | ✔️ | -| ├ Logic | ✔️ | -| ├ Routing | ✔️ | -| └ IO buffer | ✔️ | \ No newline at end of file +| FPGA Family | Gowin LittleBee | MachXO2 | +|----------------|-----------------|-----------------| +| Project | Apicula |Facade/Trellis | +| Logic Slice | ✔️ |✔️ | +| ├ LUTRAM | ❌ |❌ | +| └ ALU | ✔️ |❌ | +| IO buffer | ✔️ |✔️ | +| ├ IO standards | ✔️ |⚠️ | +| └ DDR/SERDES | ❌ |❌ | +| Block RAM | ❌ |❌ | +| DSP | ❌ |❌ | +| PLL | ❌ |❌ | +| Routing | ✔️ |✔️ | +| ├ Local | ✔️ |✔️ | +| ├ Global | ✔️ |🚧 | +| └ Long wires | ❌ |❌ (N/A) | +| Timing | ✔️ |❌ | +| ├ Logic | ✔️ |❌ | +| ├ Routing | ✔️ |❌ | +| └ IO buffer | ✔️ |❌ | + +| symbol | meaning | +|--------|--------------------------------------| +| ✔️ | complete, reliable | +| ⚠️ | nominally complete, not well-tested | +| 🚧 | incomplete | +| ❌ | unimplemented | \ No newline at end of file