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Updated FPGA family feature matrix (markdown)

YRabbit 2022-07-03 22:08:56 +10:00
parent 7596756abe
commit 1f56af09e8
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FPGA-family-feature-matrix.md

@ -12,14 +12,14 @@ The table on this page aims to keep track of which FPGA primitives are supported
| └ ALU | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (no share chain) |
| IO buffer | ✔️ |✔️ |✔️ |✔️ |✔️ |🚧 |
| ├ IO standards | ✔️ |⚠️ |✔️ |🚧 |✔️ |❌ |
| └ DDR/SERDES | ❌ |❌ |✔️ |🚧 |✔️ |❌ |
| └ DDR/SERDES | 🚧 |❌ |✔️ |🚧 |✔️ |❌ |
| Block RAM | ❌ |❌ |✔️ |✔️ |✔️ |🚧 (no TDP, no 8x20 mode) |
| DSP | ❌ |❌ |✔️ |✔️ |✔️ (up5k only) |❌ |
| PLL | ❌ |❌ |✔️ |⚠️ |✔️ |❌ |
| Routing | ✔️ |✔️ |✔️ |✔️ |✔️ |⚠️ |
| ├ Local | ✔️ |✔️ |✔️ |✔️ |✔️ |⚠️ |
| ├ Global | ✔️ |🚧 |✔️ |✔️ |✔️ |⚠️ |
| └ Long wires | ❌ |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) |
| └ Long wires | ✔️ |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) |
| Timing | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (nominal delays only) |
| ├ Logic | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (nominal delays only) |
| ├ Routing | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (nominal delays only) |