From 1f56af09e834b432a1204d0935db4ad6e17e488a Mon Sep 17 00:00:00 2001 From: YRabbit Date: Sun, 3 Jul 2022 22:08:56 +1000 Subject: [PATCH] Updated FPGA family feature matrix (markdown) --- FPGA-family-feature-matrix.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/FPGA-family-feature-matrix.md b/FPGA-family-feature-matrix.md index 1bdde16..b6fcbe7 100644 --- a/FPGA-family-feature-matrix.md +++ b/FPGA-family-feature-matrix.md @@ -12,14 +12,14 @@ The table on this page aims to keep track of which FPGA primitives are supported | └ ALU | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (no share chain) | | IO buffer | ✔️ |✔️ |✔️ |✔️ |✔️ |🚧 | | ├ IO standards | ✔️ |⚠️ |✔️ |🚧 |✔️ |❌ | -| └ DDR/SERDES | ❌ |❌ |✔️ |🚧 |✔️ |❌ | +| └ DDR/SERDES | 🚧 |❌ |✔️ |🚧 |✔️ |❌ | | Block RAM | ❌ |❌ |✔️ |✔️ |✔️ |🚧 (no TDP, no 8x20 mode) | | DSP | ❌ |❌ |✔️ |✔️ |✔️ (up5k only) |❌ | | PLL | ❌ |❌ |✔️ |⚠️ |✔️ |❌ | | Routing | ✔️ |✔️ |✔️ |✔️ |✔️ |⚠️ | | ├ Local | ✔️ |✔️ |✔️ |✔️ |✔️ |⚠️ | | ├ Global | ✔️ |🚧 |✔️ |✔️ |✔️ |⚠️ | -| └ Long wires | ❌ |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) | +| └ Long wires | ✔️ |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) | | Timing | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (nominal delays only) | | ├ Logic | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (nominal delays only) | | ├ Routing | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (nominal delays only) |