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Updated FPGA family feature matrix (markdown)

Pepijn de Vos 2022-07-03 13:17:52 +02:00
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FPGA-family-feature-matrix.md

@ -8,7 +8,7 @@ The table on this page aims to keep track of which FPGA primitives are supported
|----------------|-----------------|----------------|-----------------|----------------|----------------|-----------------|
| Project | Apicula |Facade/Trellis | Trellis | prjoxide | Icestorm | Mistral |
| Logic Slice | ✔️ |✔️ |✔️ |✔️ |✔️ |🚧 (no extended-LUT7) |
| ├ LUTRAM | ❌ |❌ |✔️ |✔️ |❌ (N/A) |🚧 (no MLAB init) |
| ├ LUTRAM | 🚧 |❌ |✔️ |✔️ |❌ (N/A) |🚧 (no MLAB init) |
| └ ALU | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (no share chain) |
| IO buffer | ✔️ |✔️ |✔️ |✔️ |✔️ |🚧 |
| ├ IO standards | ✔️ |⚠️ |✔️ |🚧 |✔️ |❌ |