yosys/techlibs/quicklogic at f925de7dc4580994aba8ebd63288c6445a156ecb - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-07 02:23:09 +02:00

Files

T

History

Emil J. Tywoniak df2ea7d788 memory: declare blackbox ports for generated RAM cells

2026-09-18 17:29:46 +02:00

..

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

CMakeLists.txt

CMake: add missing dependency edges for synth_* passes.

2026-08-06 14:48:56 +00:00

ql_bram_merge.cc

memory: declare blackbox ports for generated RAM cells

2026-09-18 17:29:46 +02:00

ql_bram_types.cc

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

ql_dsp_io_regs.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_dsp_macc.cc

pmgen: hold sigmap pointer instead of owning it

2026-09-17 15:43:54 +02:00

ql_dsp_macc.pmg

ql_dsp_macc: Tune DSP inference code

2023-12-04 15:52:02 +01:00

ql_dsp_simd.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_ioff.cc

signorm: disable in passes that use swap_names

2026-09-17 14:13:57 +02:00

synth_quicklogic.cc

synth_quicklogic: remove classic ABC mapping

2026-08-19 11:42:59 +01:00