Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
ed8b0bf9f7d51222da6d4cb7ea0e2bb2bda02653
yosys/tests/arch
T
History
nella a651db986a xilinx: Drop READ_FIRST erratum on 7 series.
2026-09-16 09:14:50 +02:00
..
analogdevices
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7
2026-07-09 08:46:46 +00:00
anlogic
synth_anlogic: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
common
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
ecp5
Merge branch 'main' into nella/latch-toggle
2026-07-08 11:41:08 +02:00
efinix
synth_efinix: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
fabulous
update tests
2026-09-01 12:47:01 +01:00
gatemate
Merge pull request #6174 from YosysHQ/lofty/abc-refactor-16
2026-09-14 16:25:07 +00:00
gowin
update tests
2026-09-01 12:47:01 +01:00
ice40
Update tests to reflect change to <inlined>
2026-09-14 10:35:11 +02:00
intel_alm
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7
2026-07-09 08:46:46 +00:00
machxo2
synth_lattice: remove classic ABC mapping
2026-08-19 11:43:00 +01:00
microchip
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
nanoxplore
fix meminit.ys
2026-09-03 13:24:37 +01:00
nexus
update tests
2026-09-01 12:47:01 +01:00
quicklogic
fix dsp.ys
2026-09-03 13:28:38 +01:00
xilinx
xilinx: Drop READ_FIRST erratum on 7 series.
2026-09-16 09:14:50 +02:00
generate_mk.py
Move output redirect to one place
2026-04-16 11:00:44 +02:00
Powered by Gitea Version: 1.27.2 Page: 85ms Template: 5ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API