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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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e8db64c609c7ae4574e66bbd475f5f10f36d7a31
yosys/tests/arch
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nella a651db986a xilinx: Drop READ_FIRST erratum on 7 series.
2026-09-16 09:14:50 +02:00
..
analogdevices
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7
2026-07-09 08:46:46 +00:00
anlogic
synth_anlogic: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
common
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
ecp5
Merge branch 'main' into nella/latch-toggle
2026-07-08 11:41:08 +02:00
efinix
synth_efinix: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
fabulous
update tests
2026-09-01 12:47:01 +01:00
gatemate
Merge pull request #6174 from YosysHQ/lofty/abc-refactor-16
2026-09-14 16:25:07 +00:00
gowin
update tests
2026-09-01 12:47:01 +01:00
ice40
Update tests to reflect change to <inlined>
2026-09-14 10:35:11 +02:00
intel_alm
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7
2026-07-09 08:46:46 +00:00
machxo2
synth_lattice: remove classic ABC mapping
2026-08-19 11:43:00 +01:00
microchip
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
nanoxplore
fix meminit.ys
2026-09-03 13:24:37 +01:00
nexus
update tests
2026-09-01 12:47:01 +01:00
quicklogic
fix dsp.ys
2026-09-03 13:28:38 +01:00
xilinx
xilinx: Drop READ_FIRST erratum on 7 series.
2026-09-16 09:14:50 +02:00
generate_mk.py
Move output redirect to one place
2026-04-16 11:00:44 +02:00
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