yosys/tests/errors/syntax_err06.v at cc7ad65a7992d82e758011ec63704b65fcb2d7d6 - yosys - Gitea: Git with a cup of tea

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Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.

2018-10-25 02:37:56 +03:00

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Verilog

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 module a;
 initial
 begin : label1
 end: label2
 endmodule