mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-04 11:29:42 +02:00
7 lines
56 B
Verilog
7 lines
56 B
Verilog
|
module a;
|
||
|
|
initial
|
||
|
|
begin : label1
|
||
|
|
end: label2
|
||
|
|
endmodule
|
||
|
|
|