Emil J. Tywoniak fbd7c249ec rtlil: remove dead verilog bindings

2026-08-31 22:13:01 +02:00

..

.gitignore

read_verilog, ast: use unified locations in errors and simplify dependencies

2025-08-11 13:34:10 +02:00

CMakeLists.txt

[core] add a cmake option to disable unit test during compilation; Use cmake_current_source for submodule integration

2026-08-21 12:09:04 -07:00

const2ast.cc

Attr file:line.

2026-07-31 10:31:44 +02:00

preproc.cc

reset default_nettype on `resetall for the lexer

2026-08-16 14:26:21 -07:00

preproc.h

reset default_nettype on `resetall for the lexer

2026-08-16 14:26:21 -07:00

verilog_error.cc

Use C++ stringf machinery in verilog_error

2025-09-12 06:21:56 +00:00

verilog_error.h

Use C++ stringf machinery in verilog_error

2025-09-12 06:21:56 +00:00

verilog_frontend.cc

reset default_nettype on `resetall for the lexer

2026-08-16 14:26:21 -07:00

verilog_frontend.h

Clean up diagnostics.

2026-07-31 10:31:44 +02:00

verilog_lexer.h

verilog_lexer: refactor

2025-08-11 13:34:10 +02:00

verilog_lexer.l

rtlil: remove dead verilog bindings

2026-08-31 22:13:01 +02:00

verilog_location.h

verilog: Fix missing sstream include

2025-08-21 08:26:20 +01:00

verilog_parser.y

rtlil: remove dead verilog bindings

2026-08-31 22:13:01 +02:00