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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 20:12:09 +02:00
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itsaflower-patch-1
yosys/techlibs/gatemate
T
History
Lofty 030e13569c synth_gatemate: remove classic ABC mapping for LUTs
2026-08-20 09:33:47 +01:00
..
.gitignore
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
arith_map.v
Fixed line endings
2026-06-23 07:17:22 +02:00
brams_init_20.vh
synth_gatemate: Initial implementation
2021-11-13 21:53:25 +01:00
brams_init_40.vh
synth_gatemate: Revise block RAM read modes and initialization
2021-11-13 21:53:25 +01:00
brams_map.v
Fixed line endings
2026-06-23 07:17:22 +02:00
brams.txt
gatemate: WRITE_THROUGH mode change
2025-04-18 14:16:02 +02:00
cells_bb.v
Fixed line endings
2026-06-23 07:17:22 +02:00
cells_sim.v
Fixed line endings
2026-06-23 07:17:22 +02:00
CMakeLists.txt
CMake: add missing dependency edges for synth_* passes.
2026-08-06 14:48:56 +00:00
gatemate_foldinv.cc
Count module output ports as consumers.
2026-08-12 10:00:30 +02:00
inv_map.v
gatemate: Add LUT tree library script
2022-06-27 10:09:48 +01:00
lut_map.v
Fixed line endings
2026-06-23 07:17:22 +02:00
make_lut_tree_lib.py
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
mul_map.v
synth_gatemate: Rename multiplier factor parameters
2021-11-13 21:53:25 +01:00
mux_map.v
Fixed line endings
2026-06-23 07:17:22 +02:00
reg_map.v
Fixed line endings
2026-06-23 07:17:22 +02:00
synth_gatemate.cc
synth_gatemate: remove classic ABC mapping for LUTs
2026-08-20 09:33:47 +01:00
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