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14768 Commits

Author SHA1 Message Date
Akash Levy f99d5a49a0
Merge pull request #15 from alaindargelas/power_activ_fix 
off by 1 bug
 2024-11-04 18:12:05 -08:00
Alain Dargelas 3cb8d6ab03 review and warnings 2024-11-04 18:11:09 -08:00
Alain Dargelas 3aea9cca79 off by 1 bug 2024-11-04 18:03:51 -08:00
Akash Levy 1cba744712 Update 2024-11-04 17:01:41 -08:00
Akash Levy 41f56efc13 Update yosys-slang dep 2024-11-04 16:48:22 -08:00
github-actions[bot] 2999f5589c Bump version 2024-11-05 00:20:31 +00:00
Akash Levy ef28e1d758 Bring back fsm 2024-11-04 12:03:56 -08:00
Akash Levy 1eb577120e Bmux unq 2024-11-04 12:03:53 -08:00
Lofty 52c231dd64
Merge pull request #4697 from georgerennie/george/zero_width_string 
frontends/ast.cc: special-case zero width strings as "\0"
 2024-11-04 15:40:04 +00:00
Lofty 3250f2b82b
Merge pull request #4700 from povik/select-list-mod 
Add `select -list-mod`
 2024-11-04 15:38:42 +00:00
Lofty 2610ccb8fa
Merge pull request #4702 from povik/cellmatch-derive-luts 
Document `cellmatch -derive_luts` option
 2024-11-04 15:38:04 +00:00
Martin Povišer d752ca4847 Fix test after option change 2024-11-04 16:26:46 +01:00
Martin Povišer cbe73c9047 cellmatch: Visit whiteboxes for `-derive_luts` 2024-11-04 14:28:46 +01:00
Martin Povišer c9ed6d8dcf cellmatch: Rename `-lut_attrs` to `-derive_luts`; document option 2024-11-04 14:28:40 +01:00
Martin Povišer 35a20da512 logger: Adjust print 2024-11-04 13:16:40 +01:00
Martin Povišer 7aa3fdab80 select: Add `-list-mod` option 2024-11-04 13:16:13 +01:00
Akash Levy 2d929f2e99 Put small back on 2024-11-01 19:38:36 -07:00
Akash Levy a2ea3c1e7a Fix colon issue 2024-11-01 17:49:29 -07:00
Akash Levy b7e51a90e4 Disable small 2024-11-01 14:57:16 -07:00
George Rennie dbfca1bdff frontends/ast.cc: special-case zero width strings as "\0" 
* Fixes #4696
 2024-11-01 17:19:28 +01:00
Emil J b2d78589e2
Merge pull request #4675 from YosysHQ/emil/pyosys-fix-segfault 
yosys: fix pyosys initialization segfault
 2024-11-01 16:40:58 +01:00
Akash Levy 4eb820a7ec Update opt_balance_tree to separate the splitfanout 2024-10-31 16:36:17 -07:00
Akash Levy 55acb4acca Fix endif 2024-10-30 09:19:16 -07:00
Akash Levy 0ffb913ef2 Fixing minor things with abc install with readline and yosys-abc copy 2024-10-30 09:14:47 -07:00
Akash Levy e50c4a47d6 Add back tests 2024-10-30 09:04:08 -07:00
Akash Levy 0a2ad64147 Makefile 2024-10-30 00:38:15 -07:00
Akash Levy b4d7812662 Add abc, some techmap passes, make opt_balance_tree only balance add/mul 2024-10-30 00:38:05 -07:00
Akash Levy 6401027ff6 Add pmux2shiftx 2024-10-29 15:00:00 -07:00
Akash Levy 62e27f5a31
Merge pull request #14 from alaindargelas/guard_sig_size_sim_val_mismatch 
Pass no_split_complex_ports to hierarchy command
 2024-10-29 13:53:43 -07:00
Alain Dargelas 4dd26490c2 help message 2024-10-29 13:52:46 -07:00
Alain Dargelas 615f523ef4 pass no_split_complex_ports to hierarchy command 2024-10-29 13:37:03 -07:00
Alain Dargelas cad46d9c66 formating 2024-10-29 10:44:16 -07:00
Alain Dargelas 3e4964a0e4 Guard against sig mismatch 2024-10-29 10:40:20 -07:00
Alain Dargelas 667a07ab56 Guard against sig mismatch 2024-10-29 10:39:21 -07:00
Akash Levy fd695c475b Update yosys-slang dep (in sync now!) 2024-10-28 22:45:15 -07:00
Akash Levy 55d4a457f5
Merge branch 'YosysHQ:main' into main 2024-10-28 17:22:47 -07:00
github-actions[bot] 8fb73e18ff Bump version 2024-10-29 00:21:12 +00:00
Akash Levy 5e606722e3 Get autoidx reset working 2024-10-28 16:30:47 -07:00
Akash Levy d63c793e72
Merge branch 'YosysHQ:main' into main 2024-10-28 11:24:55 -07:00
Lofty c07c2166f8
Merge pull request #4684 from YosysHQ/lofty/remove-qwp 
qwp: remove
 2024-10-28 09:20:03 +00:00
Martin Povišer 92fb6e205d
Merge pull request #4685 from povik/aiger2-aoi3-fix 
aiger2: Fix open-coded constants
 2024-10-28 10:15:33 +01:00
Martin Povišer 598f6c9de9 aiger2: Fix open-coded constants 2024-10-26 08:54:01 +02:00
Akash Levy cff65067cb Fix new lines 2024-10-25 20:33:43 -07:00
Akash Levy dd00b92c9f Make slices debug 2024-10-25 20:02:00 -07:00
Akash Levy 751f463994 Add fanout limit 2024-10-25 19:55:57 -07:00
Akash Levy dd17e4c133 Just do a full log 2024-10-25 19:02:38 -07:00
Akash Levy 0062d0ca5f Add more debugging 2024-10-25 18:22:40 -07:00
Akash Levy 97a804ac12 Split large constants onto new lines in verilog backend 2024-10-25 15:52:19 -07:00
Akash Levy b65ddf9aa5 No need for looping splitfanout 2024-10-25 15:51:46 -07:00
Akash Levy 038c562493 VHDL support fix 2024-10-25 11:32:52 -07:00