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72 Commits

Author SHA1 Message Date
Stan Lee 91345c2283 warning msg and address spaces 2026-04-01 09:21:02 -07:00
Stan Lee b6f118091c Support for N-dimensional arrays in simulation 2026-03-31 12:50:36 -07:00
Stan Lee 857f356f1f remove ambiguity in implementation 2026-03-30 12:26:44 -07:00
Stan Lee 01f0fd751f fixes for arrays 2026-03-30 12:13:50 -07:00
Stan Lee e5d3bb954e correction 2026-03-16 12:05:27 -07:00
Stan Lee bcf71dea85 dump the number of scopes/signals in the search space 2026-03-13 11:15:46 -07:00
Stan Lee b7984f12f8 greptile 2026-03-06 12:19:17 -08:00
Stan Lee 1592125e71 fix err 2026-03-06 10:36:29 -08:00
Stan Lee 69145403df more updates 2026-03-06 10:32:28 -08:00
Stan Lee c9330dc36f oop 2026-03-06 10:30:49 -08:00
Stan Lee 20c1f3212f cleaner with warning 2026-03-06 10:23:31 -08:00
Stan Lee cb3853fca0 improvements to autoscope 2026-03-06 09:51:45 -08:00
Stan Lee a01d0b2935 autoscope supports top-level fork scope ports 2026-03-04 10:25:53 -08:00
Akash Levy 958f1c608a
Merge pull request #116 from Silimate/autoscope 
Autoscope
 2026-03-03 20:49:13 -08:00
Stan Lee 7e8331dd95 greptile 2026-03-03 15:15:26 -08:00
Stan Lee a1470e14fe typos 2026-03-02 12:57:37 -08:00
Stan Lee a449e6ab38 always dump available scopes 2026-03-02 12:19:09 -08:00
Stan Lee 83e05a6509 fixes 2026-03-02 12:07:59 -08:00
Stan Lee da25b800bc finalized 2026-03-02 11:05:44 -08:00
Stan Lee 6594ff508f improvement 2026-03-02 00:42:34 -08:00
Stan Lee c459a74c13 autoscoping 2026-03-01 15:39:35 -08:00
Stan Lee 8ee71ddc7f bugfix 2026-02-27 12:19:14 -08:00
Stan Lee 93af5a5232 in order 2026-02-27 12:17:43 -08:00
Stan Lee c42d2c2d03 support for nested structs 2026-02-27 11:54:43 -08:00
Stan Lee d36e2f7d17 resolve accidental change 2026-02-27 11:40:13 -08:00
Stan Lee 03ce300b49 another indent 2026-02-27 11:29:31 -08:00
Stan Lee fa1267e0cb fix indents 2026-02-27 11:27:37 -08:00
Stan Lee ae3b9b74e2 ready 2026-02-27 11:25:10 -08:00
Stan Lee 48894488f1 better method for assigning fsthandles 2026-02-27 11:25:10 -08:00
Stan Lee 0aaca679ce better but not ideal 2026-02-27 11:25:10 -08:00
Stan Lee 5bdc2d3451 working implementation that i will improvee further 2026-02-27 11:25:10 -08:00
Akash Levy 608730652b Remove fstdata header 2025-11-29 11:47:41 -05:00
Akash Levy 652a9a63b2 Update to latest and fix all disabled tests 2025-09-28 01:33:08 -07:00
Robert O'Callahan 1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Akash Levy f5cb0c328f Bump Yosys to latest 2025-09-13 04:35:52 -07:00
Robert O'Callahan e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Akash Levy 1b3375d8df Merge upstream in 2025-09-09 05:50:48 -07:00
Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Akash Levy 1f00bf0057 Bump yosys to latest 2025-05-15 14:44:26 -07:00
Krystine Sherwin afd5bbc7fa
fstdata.cc: Fix last step 
Includes test file for sanity checking simulation steps.
 2025-05-12 13:18:19 +12:00
Krystine Sherwin d0b9a0cb98
sim.cc: Move cycle check 
Calling `throw dst_end_of_data_exception()` when the desired number of cycles has been reached means that the fst reader can't tidy up after itself and leads to memory leaks.
This doesn't happen when the `-stop` flag is used because the `Yosys::FstData` struct tracks the end time and skips the outer callback if the simulation has gone past the desired end time.
Move cycle checking into the inner callback along with the time checking means that the outer callback no longer needs to throw an exception in order to stop checking further values, while still allowing the fst reader to finish reading and deallocate memory.
 2025-05-12 12:48:01 +12:00
Akash Levy cddfd1f12a Formatting 2025-02-14 04:26:26 -08:00
Alain Dargelas 0965ee2859 Tmp file for vcd2fst 2025-01-21 16:05:24 -08:00
N. Engelhardt 2de9f00368
Merge pull request #4620 from RCoeurjoly/fix-vcd-parsing-ghdl-var-spacing 2024-11-06 16:29:07 +01:00
Roland Coeurjoly 5ea2c6e6e5 Assume x values for missing signal data in FST 
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-10-02 12:08:48 +02:00
Roland Coeurjoly 76c615b2ae Fix: handle VCD variable references with and without whitespace 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-10-01 11:51:20 +02:00
Miodrag Milanovic 6574553189 Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
Jannis Harder 68d52cb1b1 fstdata: Update past_data before end_time callback 
Required to make the '-at' parameter work.
 2022-11-07 12:32:23 +01:00
Jannis Harder 3477f2d00b fstdata: Handle square/angle bracket replacemnt, change memory handling 
When writing VCDs smtbmc replaces square brackets with angle brackets to
avoid the issues with VCD readers misinterpreting such signal names.

For memory addresses it also uses angle brackets and hexadecimal
addresses, while other tools will use square brackets and decimal
addresses.

Previously the code handled both forms of memory addresses, assuming
that any signal that looks like a memory address is a memory address.
This is not the case when the user uses regular signals whose names
include square brackets _or_ when the verific frontend generates such
names to represent various constructs.

With this change all angular brackets are turned into square brackets
when reading the trace _and_ when performing a signal lookup. This means
no matter which kind of brackets are used in the design or in the VCD
signals will be matched. This will not handle multiple signals that are
the same apart from replacing square/angle brackets, but this will cause
issues during the VCD writing of smtbmc already.

It still uses the distinction between square and angle brackets for
memories to decide whether the address is hex or decimal, but even if
something looks like a memory and is added to the `memory_to_handle`
data, the plain signal added to `name_to_handle` is used as-is, without
rewriting the address.

This last change is needed to successfully match verific generated
signal names that look like memory addresses while keeping memories
working at the same time. It may cause regressions when VCD generation
was done with a design that had memories but simulation is done with a
design where the memories were mapped to registers. This seems like an
unusual setup, but could be worked around with some further changes
should this be required.
 2022-11-07 12:30:08 +01:00
Mohamed A. Bamakhrama 1822be8792 Observe $TMPDIR variable when creating tmp files 
POSIX defines $TMPDIR as containing the pathname of the directory where
programs can create temporary files. On most systems, this variable points to
"/tmp". However, on some systems it can point to a different location.
Without respecting this variable, yosys fails to run on such systems.

Signed-off-by: Mohamed A. Bamakhrama <mohamed@alumni.tum.de>
 2022-05-27 15:06:53 +02:00