mirror of https://github.com/YosysHQ/yosys.git
improvement
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parent
c459a74c13
commit
6594ff508f
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@ -308,10 +308,10 @@ std::string FstData::autoScope(Module *topmod) {
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log("Trying port-based scope matching...\n");
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// Map port name to their bit widths (RTL reference point)
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dict<std::string, int> ports;
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dict<std::string, int> ports2widths;
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for (auto wire : topmod->wires()) {
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if (wire->port_input || wire->port_output) {
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ports[RTLIL::unescape_id(wire->name)] = wire->width;
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ports2widths[RTLIL::unescape_id(wire->name)] = wire->width;
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}
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}
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@ -322,15 +322,16 @@ std::string FstData::autoScope(Module *topmod) {
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// Strip array '[]' notation from variable name
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std::string var_name = var.name;
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log("Checking variable: %s with scope: %s\n", var_name.c_str(), var.scope.c_str());
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size_t bracket = var_name.find('[');
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if (bracket != std::string::npos) {
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var_name = var_name.substr(0, bracket);
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}
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// Check if this variable name matches one of our port names
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if (ports.count(var_name)) {
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if (ports2widths.count(var_name)) {
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// Also check if width matches
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if (ports[var_name] == var.width) {
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if (ports2widths[var_name] == var.width) {
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scope_found_ports[var.scope].insert(var_name);
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}
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}
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@ -342,9 +343,9 @@ std::string FstData::autoScope(Module *topmod) {
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const std::set<std::string>& found = entry.second;
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// Check if all port names exist in this scope
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if (found.size() == ports.size()) {
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if (found.size() == ports2widths.size()) {
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log("Auto-discovered scope: %s (matched all %d ports by name)\n",
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scope.c_str(), (int)ports.size());
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scope.c_str(), (int)ports2widths.size());
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return scope;
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}
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}
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