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17035 Commits

Author SHA1 Message Date
Gary Wong 4ffd05af6f verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
 2025-08-11 13:34:10 +02:00
garytwong 105a3cd32d verilog: fix string literal regular expression (#5187) 
* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 0a5aa4c78b docs: fix verilog frontend internals 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 42b5c14e35 read_verilog, ast: use unified locations in errors and simplify dependencies 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak e6e680cd62 readme, verilog_parser: bison 3.8 and ubuntu 22.04 example 2025-08-11 13:34:10 +02:00
Krystine Sherwin 0f7080ebf8 dpicall.cc: Fix sans-plugin function call 2025-08-11 13:34:10 +02:00
Krystine Sherwin f4016d96cc Makefile: Add flex lib/include for brew 2025-08-11 13:34:10 +02:00
Krystine Sherwin d2573f168d preproc.cc: Use full path for generated file 
Fixes out-of-tree builds.
 2025-08-11 13:34:10 +02:00
Krystine Sherwin 69f2f3ca81 docs/verilog_frontend.rst: Fix indentation 2025-08-11 13:34:10 +02:00
Krystine Sherwin 8e89eab9a2 preproc depends on parser 2025-08-11 13:34:10 +02:00
Krystine Sherwin 2b7b09b81a Add libfl-dev 
Should fix the missing `<FlexLexer.h>` error.
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 27899180a3 fixup! fixup! ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 87352f97b2 fixup! ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak ecec9a760b ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 8bf750ecbb neater errors, lost in the sauce of source 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak b3bf588966 ast, read_verilog: refactoring 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 84f0c5da73 ast: fix new memory safety bugs from rebase 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 4a00169452 ast: ownership for string values 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak c8e0ac0c61 ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak f27309136f Revert "verilog: fix string literal regular expression (#5187)" 
This reverts commit 834a7294b7.
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 36491569d2 Revert "verilog: add support for SystemVerilog string literals." 
This reverts commit 5feb1a1752.
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 98b3316f55 Revert "verilog: fix parser "if" memory errors." 
This reverts commit 34a2abeddb.
 2025-08-11 13:34:09 +02:00
Akash Levy d0ab898e88
Merge branch 'YosysHQ:main' into main 2025-08-10 22:46:15 -07:00
Miodrag Milanović 8c71226d00
Merge pull request #5276 from YosysHQ/krys/bump_nix 
Bump nix on CI
 2025-08-09 07:12:22 +02:00
github-actions[bot] 0d4585dd5f Bump version 2025-08-09 00:24:43 +00:00
KrystalDelusion 6c84c4a4fc
extra-builds.yml: Bump nix 2025-08-09 11:19:24 +12:00
KrystalDelusion 1ae82d7b9d
Merge pull request #5233 from YosysHQ/krys/equiv_assume 
Assumptions for equiv_*
 2025-08-09 10:39:04 +12:00
Akash Levy 0354098c08
Merge pull request #84 from neildeo05/sim_and_clockgate 
add clockgate to makefile, add Density to sim pass
 2025-08-08 11:08:41 -07:00
Neil Deo 1122b92247 Use hardtabs 2025-08-08 11:08:20 -07:00
Neil Deo 07b54dff2b fix bad indentation 2025-08-08 10:39:25 -07:00
Akash Levy 613dfcc6b4
Merge branch 'YosysHQ:main' into main 2025-08-08 10:37:08 -07:00
Emil J d68d28d05e
Merge pull request #5183 from YosysHQ/emil/test-diagnostics 
logger: add -expect types prefix-log, prefix-warning, prefix-error
 2025-08-08 14:46:25 +02:00
Akash Levy 7a055dbe32 Use restricted multiport RAMs in Verific 2025-08-08 02:44:24 -07:00
Emil J 94d3b3eb5a
Merge pull request #5273 from YosysHQ/emil/krys-equiv_assume-refactor 
equiv_simple: refactor
 2025-08-08 10:52:15 +02:00
Hongce Zhang 76e507f307 update verilog_backend according to Github comments 2025-08-08 16:17:37 +08:00
Akash Levy 3311056d81 Revert "Revert some vhdl stuff" 
This reverts commit 6a9102346a.
 2025-08-08 01:16:49 -07:00
Akash Levy 6a9102346a Revert some vhdl stuff 2025-08-08 01:05:57 -07:00
Akash Levy 0e50fd3b74 Restricted multiport 2025-08-08 00:37:20 -07:00
Akash Levy 61bac59238 Update Verific to handle large memories better 2025-08-07 19:38:30 -07:00
Neil Deo 88816e390e add clockgate to makefile, add Density to sim pass 2025-08-07 18:07:15 -07:00
Akash Levy c4b20f14ea
Merge branch 'YosysHQ:main' into main 2025-08-07 17:58:29 -07:00
Krystine Sherwin e02f4469c0
equiv_simple: Avoid std::array 
VS build currently failing with `error C2641: cannot deduce template arguments for 'std::array'`.
Changing to `std::array<Cone, 2>` gives `error C2027: use of undefined type` instead.
 2025-08-08 12:37:38 +12:00
github-actions[bot] c9558b3d4f Bump version 2025-08-08 00:26:50 +00:00
Akash Levy 77be4d7be7 Bump Yosys to latest 2025-08-07 17:22:25 -07:00
Emil J. Tywoniak fcd9f98245 equiv_simple: refactor 2025-08-08 01:35:33 +02:00
KrystalDelusion 7f0e864d44
Merge pull request #5265 from bhagwat-rahul/fix-package-import 
Support package import
 2025-08-08 09:32:54 +12:00
Emil J 21b9c8e4c6
Merge pull request #5236 from rocallahan/const-lookup 
Make `dict` and `pool` const lookup methods never rehash the hashtable
 2025-08-07 11:43:39 +02:00
Emil J 1e58443397
Merge pull request #5264 from YosysHQ/krys/raise_error_always 
raise_error: Add -always
 2025-08-07 11:43:04 +02:00
Miodrag Milanovic e6059d042d Next dev cycle 2025-08-07 09:20:45 +02:00
Miodrag Milanovic 9c447ad9d4 Release version 0.56 2025-08-07 07:59:29 +02:00