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18391 Commits

Author SHA1 Message Date
AdvaySingh1 b53acb0ff0 Added pass in Makefile.inc 2026-02-10 14:33:17 -08:00
AdvaySingh1 b4ef420c3f Added inital SAT based clock gating file 2026-02-10 14:02:15 -08:00
Krystine Sherwin 9f30f0e7d6
test-build: Don't rebuild OBJS 2026-02-10 15:34:47 +13:00
Krystine Sherwin 030e495c8b
test-build: Build and cache libyosys.so 2026-02-10 15:05:17 +13:00
github-actions[bot] a6e33d9916 Bump version 2026-02-10 00:38:43 +00:00
Emil J d2f7d3cf63
Merge pull request #5665 from rocallahan/abc-tmp-path 
Sanitize ABC global and per-run temporary directory names in logs
 2026-02-09 23:26:57 +01:00
Emil J. Tywoniak ff9cd0eed7 Makefile: test target requires unit-test, add vanilla-test for old test target 2026-02-09 23:21:24 +01:00
Gus Smith b04948a8cd Simplify test 2026-02-09 09:38:45 -08:00
Gus Smith 6f6fa49d3c Typo 2026-02-09 09:05:56 -08:00
Rowan Goemans b8ee50d77f kernel/celledges: cover more cell types 2026-02-09 14:13:40 +01:00
Akash Levy f8a095e404
Merge pull request #105 from Silimate/negopt-fixes 
fixed edge cases in negopt passes, fixed cell naming inconsistencies
 2026-02-08 23:37:04 -08:00
Akash Levy ee46f498e1
Update negopt.cc 2026-02-07 17:54:16 -08:00
Gus Smith 1502e23371 Set solver from scratchpad or command line 2026-02-06 19:26:32 -08:00
Gus Smith b2f9ac4fb5 Check for dimacs nullptr on file creation+fn call 2026-02-06 18:18:03 -08:00
Gus Smith 2bb352a861 Missing newline 2026-02-06 17:45:00 -08:00
Gus Smith f062a0c8d6 Typo 2026-02-06 17:26:08 -08:00
tondapusili 6bb43f109c fixed edge cases in negopt passes, fixed cell naming inconsistencies 2026-02-06 16:38:55 -08:00
Robert O'Callahan 34f8582725
Sanitize ABC global and per-run temporary directory names in logs 2026-02-07 12:12:13 +13:00
Akash Levy dc1847f89a
Merge pull request #104 from Silimate/mux_push_implementation 
mux_push implementation
 2026-02-05 17:55:51 -08:00
tondapusili d592f312ab mux_push implementation 2026-02-05 16:49:59 -08:00
Akash Levy 5f7658ca7c
Merge branch 'YosysHQ:main' into main 2026-02-05 13:10:34 -08:00
Emil J 1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift 
opt_expr: fix const lhs of $pow to $shl
 2026-02-05 13:09:01 +01:00
Akash Levy f74ac17a5f Undo the terrible upstream changes that break everything... 2026-02-04 22:26:06 -08:00
Akash Levy 09fd53aaae Update abc 2026-02-04 17:01:27 -08:00
github-actions[bot] 0640a5904b Bump version 2026-02-05 00:33:25 +00:00
Akash Levy d3ab45c2fa
Merge branch 'YosysHQ:main' into main 2026-02-04 15:53:43 -08:00
Akash Levy dbeeb7a7cf
Merge pull request #98 from Silimate/nr_cleanup 
Nr cleanup
 2026-02-04 15:49:01 -08:00
AdvaySingh1 8d22f6d7e1 Merged with main 2026-02-04 13:00:22 -08:00
AdvaySingh1 607ef02339 Added abc_max_node_retention_origins flag in AbcConfig struct 2026-02-04 12:12:04 -08:00
AdvaySingh1 16b5a8e350 ABC: added -M flag for nMaxOrigins 2026-02-04 12:02:31 -08:00
AdvaySingh1 43027720d2 Fixed no sources log error to only output error if node_retention mode is on 2026-02-04 10:22:24 -08:00
Emil J 8bbde80e02
Merge pull request #5631 from rocallahan/cleanup-compare-signals 
Clean up `compare_signals()` in `opt_clean`
 2026-02-04 17:45:05 +01:00
Emil J 2aa0e1d009
Merge pull request #5629 from rocallahan/remove-zero-wires 
Avoid scanning entire module in `Module::remove()` if there are no wires to remove
 2026-02-04 17:44:24 +01:00
Emil J 992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort 
Remove `Design::sort()` calls from optimization passes
 2026-02-04 16:55:56 +01:00
Akash Levy 48e7b5a167 Let's go back to a simpler time for abc... 2026-02-04 04:33:19 -08:00
Akash Levy c57c49873e Please just stop modifying yosys... 2026-02-04 03:48:58 -08:00
Akash Levy ea6b968618
Merge pull request #102 from Silimate/merge2 
Merge2
 2026-02-04 02:54:00 -08:00
Akash Levy 241852eebd Test merge from upstream 2026-02-04 02:07:01 -08:00
Akash Levy af7e124c26
Merge pull request #101 from Silimate/yosys_abc_test1 
Small abc update to see what happens
 2026-02-04 01:45:56 -08:00
Akash Levy dd08ba75bc
Merge pull request #100 from Silimate/negopt-pass-pr 
Add negopt pass with comprehensive pattern matching
 2026-02-04 01:44:45 -08:00
Akash Levy 3bffeee622
Merge pull request #99 from Silimate/sim 
Activity annotation will use timescale from VCD
 2026-02-04 01:26:25 -08:00
Akash Levy 715e062bcd Merge branch 'main' into negopt-pass-pr 2026-02-04 00:15:53 -08:00
Akash Levy 0e0740a3a0
Remove unnecessary blank line in abc.cc 2026-02-04 00:08:42 -08:00
Akash Levy 33bcfe26dd Merge branch 'main' into sim 2026-02-03 23:57:24 -08:00
Miodrag Milanović 776b4d06a6
Merge pull request #5669 from YosysHQ/release/v0.62 
Release version 0.62
 2026-02-04 08:55:31 +01:00
Akash Levy 23ed2ef523 Small abc update to see what happens 2026-02-03 23:55:25 -08:00
Miodrag Milanovic ddfa34d743 Next dev cycle 2026-02-04 08:54:38 +01:00
Akash Levy 807df40422 Undo the weird abc changes 2026-02-03 23:21:48 -08:00
Robert O'Callahan 7326bb7d66
Only reuse ABC processes if we're using yosys-abc and it was built with ENABLE_READLINE 
(cherry picked from commit 5054fd17d7b70f2df97360bb0f0cc1c92a6ffe72)
 2026-02-04 17:19:10 +13:00
tondapusili 643427d9c9 Add negopt pass with comprehensive pattern matching 
This commit introduces the negopt pass with pre/post optimization modes
for handling negation patterns in arithmetic circuits.

Pre-optimization patterns (expose for tree balancing):
- manual2sub: (a + ~b) + 1 → a - b
- sub2neg: a - b → a + (-b)
- negexpand: -(a + b) → (-a) + (-b) [with output width fix]
- negneg: -(-a) → a
- negmux: -(s ? a : b) → s ? (-a) : (-b)

Post-optimization patterns (cleanup/rebuild):
- negrebuild: (-a) + (-b) → -(a + b)
- muxneg: s ? (-a) : (-b) → -(s ? a : b)
- neg2sub: a + (-b) → a - b

All patterns use nusers() for fanout checking (standard Yosys style).
Comprehensive test coverage with positive/negative cases and formal
verification via equiv_opt.
 2026-02-03 17:21:21 -08:00