luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
16,690 Commits 131 Branches 66 Tags 62 MiB
Commit Graph

4833 Commits

Author SHA1 Message Date
Robert O'Callahan 914e14946d Implement design_equal command 2025-12-21 21:47:40 +00:00
N. Engelhardt 45d654e2d7 avoid merging formal properties 2025-12-17 20:25:24 +01:00
Krystine Sherwin 5b317ee03c
sim.cc: Check eval err 
Some cells (e.g. $macc_v2) are marked evaluable, but will raise an abort if called with `CellTypes::eval()`.
Instead of falling through to the abort, we can pass a pointer to a boolean to check for errors.
Use said check to catch `CellTypes::eval()` errors and treat them as unevaluable but otherwise continue.
Reflows the series of if checks into `if ... else if ... else` so that we can check for errors and set state in one place.
 2025-12-15 12:08:07 +13:00
Krystine Sherwin 9d3d8bf502
Switch posix_spawn to posix_spawnp 2025-12-15 09:40:04 +13:00
Emil J f003eca615
Merge pull request #5526 from YosysHQ/emil/fix-cellaigs-function-arg-eval-order 
cellaigs: fix function argument evaluation order
 2025-12-12 10:00:09 +01:00
Robert O'Callahan 638e904f91 Remove cover() coverage tracking 2025-12-04 16:27:13 +01:00
Krystine Sherwin 9ec361beab
test_cell.cc: Generate .aag for all compatible cells 
Skips (with warning) on cells that didn't convert to avoid `write_aiger` from raising an error.
 2025-12-02 14:03:36 +13:00
Emil J 9871e9b17e
Merge pull request #5496 from YosysHQ/emil/liberty-flop-loops 
read_liberty: support loopy retention cells
 2025-12-01 22:50:20 +01:00
Emil J 510f9ef63d
Merge pull request #5499 from mikesinouye/abc_new 
Enable abc_new pass when not in NDEBUG
 2025-11-24 16:57:29 +01:00
Emil J. Tywoniak e8cbc92462 abc_new: sorted -> is_sorted 2025-11-24 11:46:09 +01:00
Robert O'Callahan 53614a37a1 Use `Tcl_Size` instead of `int` to fix build errors 
Fixes these build errors I'm getting locally with `tcl-devel-9.0.0-7.fc42.x86_64`.
I guess Tcl 9 broke this.

```
passes/cmds/sdc/sdc.cc:438:6: error: no matching function for call to 'Tcl_ListObjLength'
  438 |         if (Tcl_ListObjLength(interp, listObj, &listLength) == TCL_OK) {
      |             ^~~~~~~~~~~~~~~~~
/usr/include/tclDecls.h:1788:13: note: candidate function not viable: no known conversion from 'int *' to 'Tcl_Size *' (aka 'long *') for 3rd argument
 1788 | EXTERN int              Tcl_ListObjLength(Tcl_Interp *interp,
      |                         ^
 1789 |                                 Tcl_Obj *listPtr, Tcl_Size *lengthPtr);
      |                                                   ~~~~~~~~~~~~~~~~~~~
passes/cmds/sdc/sdc.cc:446:8: error: no matching function for call to 'Tcl_ListObjLength'
  446 |                         if (Tcl_ListObjLength(interp, subListObj, &subListLength) == TCL_OK) {
      |                             ^~~~~~~~~~~~~~~~~
/usr/include/tclDecls.h:1788:13: note: candidate function not viable: no known conversion from 'int *' to 'Tcl_Size *' (aka 'long *') for 3rd argument
 1788 | EXTERN int              Tcl_ListObjLength(Tcl_Interp *interp,
      |                         ^
 1789 |                                 Tcl_Obj *listPtr, Tcl_Size *lengthPtr);
      |                                                   ~~~~~~~~~~~~~~~~~~~
```
 2025-11-24 18:46:56 +13:00
Mike Inouye 615e338acd
Fix abc_new pass when not in NDEBUG 2025-11-21 14:10:05 -08:00
Robert O'Callahan e33ca17388 Force a newline to appear before YOSYS_ABC_DONE 2025-11-21 03:50:07 +00:00
Emil J. Tywoniak b3112bf025 filterlib: prefer using precedence over unsynthesizable verilog 2025-11-21 00:43:54 +01:00
Emil J. Tywoniak 6eb9e823e0 sdc: use Tcl memory management functionality 2025-11-20 00:21:15 +01:00
Emil J 2eff366e8c
Merge branch 'main' into emil/sdc_expand 2025-11-19 16:29:37 +01:00
Emil J. Tywoniak 920f4793fb sdc: error on unknown getters 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 229123eb87 sdc: disable without YOSYS_ENABLE_TCL 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 033a2d5a67 sdc: remove vestigial code for tracked constraint followup work 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak f56e121ddb sdc: add help 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 650392d4ec sdc: specialize stubs for the call graph 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 224ed524fa sdc: move to directory 2025-11-19 15:26:01 +01:00
Emil J. Tywoniak 94dd248dfb sdc: graph mode only 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 8a54e51300 sdc: add -keep_hierarchy 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak d4228efae8 sdc: keep_hiearchy 2025-11-19 15:25:24 +01:00
Emil Jiří Tywoniak 075237f73b sdc: refactor more 2025-11-19 15:25:24 +01:00
Emil Jiří Tywoniak 48ff9d4950 sdc: refactor find_matching 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak ae1235210d sdc: functional graph 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak c6491629d8 sdc: start graph 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 24a6412ea8 sdc: bit selections 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 21c68e0022 sdc: unknown handler experiment 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 420a083d9b sdc: simple mode, remove per-tool stubs 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 834125a076 sdc: return resolved patterns 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak dc48ceadd9 sdc: collect strictly matching objects 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 9a3c7f70ad sdc: stubs SDC commands supported by OpenSTA 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak c26aa3186d sdc: collect design objects 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak c1c6ec1266 sdc: stubs SDC commands supported by Vivado 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 5a798b64ef sdc: separate out 2025-11-19 15:25:22 +01:00
Emil J. Tywoniak 9a5465bc83 icell_liberty: simplify 2025-11-19 15:20:50 +01:00
Emil J. Tywoniak cee3d0b598 icell_liberty: refactor and add help 2025-11-19 15:20:50 +01:00
Emil J. Tywoniak e4e32d7966 icell_liberty: flop harder 2025-11-19 15:20:50 +01:00
Emil J. Tywoniak c2c9506f4f icell_liberty: flops 2025-11-19 15:20:50 +01:00
Emil J. Tywoniak b3ead7e47d icell_liberty: start 2025-11-19 15:20:50 +01:00
Miodrag Milanović 4bfdc62f65
Merge pull request #5472 from Anhijkt/arst-fsm-handling 
fsm_detect: add adff detection
 2025-11-14 13:47:08 +01:00
Robert O'Callahan 8c2984dc5f Fix AbcModuleState::remap_name() to avoid calling IdString::c_str() 2025-11-12 11:52:04 +01:00
Robert O'Callahan 325b27f43a Avoid calling IdString::c_str() in opt_clean 2025-11-12 11:52:04 +01:00
Robert O'Callahan 54bde15329 Implement IdString garbage collection instead of refcounting. 2025-11-12 11:52:04 +01:00
Emil J. Tywoniak 967e91aa73 libparse: fix parsing and memory safety of quoted values 2025-11-11 13:44:50 +01:00
Emil J 365c6753c4
Merge pull request #5453 from rocallahan/sigspec-onechunk 
Make `SigSpec` const methods multithreading-compatible
 2025-11-10 17:48:42 +01:00
Robert O'Callahan 3f7af10eda Make SigSpec::chunks() return an object that can be iterated over without packing the SigSpec 2025-11-07 15:54:54 +00:00
KrystalDelusion 24b69cabaa
Merge pull request #5422 from YosysHQ/krys/SVI_support 
Catch partial support of SVI
 2025-11-07 11:16:07 +13:00
Anhijkt 7d10a72490 fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
Emil J a16fc9b4f3
Merge pull request #5467 from YosysHQ/emil/liberty-unquoted-expressions 
libparse: support unquoted expressions
 2025-11-06 19:45:17 +01:00
Emil J. Tywoniak fdcc4c1507 libparse: remove leftover comments 2025-11-06 13:30:09 +01:00
Emil J a2aeef6c96
Merge pull request #5461 from rocallahan/reset-abc-config 
Fix regression in configuring ABC techmapping
 2025-11-06 11:58:04 +01:00
Robert O'Callahan 0f770285f3 Move global ABC configuration variables into AbcConfig and initialize them properly 2025-11-05 13:56:04 +00:00
Emil J. Tywoniak 90553267b0 libparse: fix quoting and negedge in filterlib -verilogsim 2025-11-05 14:13:58 +01:00
Emil J. Tywoniak 504b668ea6 libparse: fix verilogsim negedge 2025-11-05 13:49:05 +01:00
Emil J. Tywoniak bf29f6dc11 libparse: tolerate closing quotes in expression parsing 2025-11-05 13:06:09 +01:00
Emil J. Tywoniak 4fac7a1b20 libparse: fix space before closing paren in expressions 2025-11-05 13:05:56 +01:00
Emil J. Tywoniak 547e254a9b libparse: parse expressions in filterlib 2025-11-05 13:05:56 +01:00
Emil J. Tywoniak 66d8fc5c28 libparse: quirk-compatibility for unquoted boolean expression strings 2025-11-05 11:00:25 +01:00
Martin Povišer 5fa7feccd3 timeest: Add top ports launching/sampling 2025-11-03 14:21:28 +01:00
Emil J. Tywoniak b2fe335b2d dfflibmap: fix next_state inversion propagation for DFF flops by inverting reset value polarity 2025-10-28 13:56:28 +01:00
Miodrag Milanović 2613c1c0a9
Merge pull request #5438 from cr1901/posix-bugpoint 
Add sys/wait.h header to bugpoint to bring in constants.
 2025-10-22 12:40:26 +02:00
William D. Jones 311a2739f6 Add sys/wait.h header to bugpoint to bring in constants. 2025-10-20 19:50:18 -04:00
Jannis Harder 6a0ee6e4fb Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00
Miodrag Milanovic f11a61b32b sim: Make cycle width small as possible and configurable 2025-10-16 11:37:44 +02:00
Miodrag Milanovic db8c1878a0 fix dlopen using fs:path with mingw 2025-10-16 08:30:43 +02:00
Mohamed Gaber dce70abd94
plugins: support Windows path delimiters 2025-10-15 15:53:44 +03:00
Mohamed Gaber e86797f029
plugins: add search path 
This uses the environment variable `YOSYS_PLUGIN_PATH` to provide multiple colon-delimited search paths for native plugins in a similar manner to `PATH` for executables and `PYTHONPATH` for Python modules.

This addresses https://github.com/YosysHQ/yosys/issues/2545, allowing Yosys to be better packaged in non-FHS environments such as Nix.
 2025-10-15 14:13:25 +03:00
Krystine Sherwin 10a55119a9
hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
Krystine Sherwin 5d2d544109
hierarchy.cc: Don't segfault 2025-10-15 09:38:43 +13:00
Krystine Sherwin 7bb0a1913e
hierarchy.cc: Raise error on positional interface 
Add test to check that it does error.
 2025-10-15 09:10:33 +13:00
Emil J a5960ce515
Merge pull request #5197 from YosysHQ/emil/opensta-verilog-export 
OpenSTA verilog compatibility
 2025-10-14 16:46:37 +02:00
Emil J. Tywoniak e9aedf505c chtype: replace publish pass with chtype -publish_icells 2025-10-14 15:01:48 +02:00
Emil J. Tywoniak e5edd2acdb sort: init 2025-10-13 17:32:26 +02:00
Emil J. Tywoniak c46df9ffdc box_derive: rename -apply to -apply_derived_type 2025-10-13 17:24:32 +02:00
Emil J. Tywoniak d7cea2c35c box_derive: add -apply 2025-10-13 17:24:32 +02:00
Emil J. Tywoniak 7d8f92e198 publish: add pass for renaming private cell types to public 2025-10-13 17:24:32 +02:00
Emil J 9a12d92551
Merge pull request #5386 from YosysHQ/emil/liberty-glob-all 
Expand wildcards in Liberty file consumers
 2025-10-09 20:21:48 +02:00
Miodrag Milanović ba1a347d59
Merge pull request #5370 from donn/pyosys_pybind11 
pyosys: rewrite using pybind11
 2025-10-08 13:07:59 +02:00
Miodrag Milanović 4cdaac003f
Merge pull request #3991 from adrianparvino/alumacc-sign 
alumacc: merge independent of sign
 2025-10-08 13:02:10 +02:00
Jannis Harder 2c94ca85d9 abc_new: Avoid bufnorm helper cell churn 
We were performing the helper passes `abc9_ops -replace_zbufs` and
`abc9_ops -restore_zbufs` for every module, but those passes act on the
full design (and can't be applied entirely selectively due to entering
and leaving bufnorm).

This lead to an explosive creation of a lot of redundant bufnorm helper
cells that would have been cleaned up by `clean` but that never ran.
Instead we now run each helper pass once, one before and one after
iterating over the selected modules. This limits the number of bufnorm
helper cells.
 2025-10-07 18:05:28 +02:00
Krystine Sherwin da2e021e3b abc9.cc: Use -r for &dch 
Avoids "ABC: The command has to terminate. Boxes are not in a topological order." error during `&if`.
 2025-10-06 14:07:40 +01:00
Mohamed Gaber 447a6cb3f0
misc: `WITH_PYTHON` -> `YOSYS_ENABLE_PYTHON` 
For consistency.

Also trying a new thing: only rebuilding objects that use the pybind11 library. The idea is these are the only objects that include the Python/pybind headers and thus the only ones that depend on the Python ABI in any capacity, so other objects can be reused across wheel builds. This has the potential to cut down build times.
 2025-10-03 11:54:44 +03:00
Mohamed Gaber 88be728353
pyosys: rewrite using pybind11 
- Rewrite all Python features to use the pybind11 library instead of boost::python.
  Unlike boost::python, pybind11 is a header-only library that is just included by Pyosys code, saving a lot of compile time on wheels.
- Factor out as much "translation" code from the generator into proper C++ files
- Fix running the embedded interpreter not supporting "from pyosys import libyosys as ys" like wheels
- Move Python-related elements to `pyosys` directory at the root of the repo
- Slight shift in bridging semantics:
  - Containers are declared as "opaque types" and are passed by reference to Python - many methods have been implemented to make them feel right at home without the overhead/ambiguity of copying to Python and then copying back after mutation
  - Monitor/Pass use "trampoline" pattern to support virual methods overridable in Python: virtual methods no longer require `py_` prefix
- Create really short test set for pyosys that just exercises basic functionality
 2025-10-03 11:54:44 +03:00
Emil J 7719beb4ae
Merge pull request #5349 from rocallahan/cleanup-hashops 
Reduce hashops verbiage in `OptMergePass`
 2025-09-30 19:34:44 +02:00
Jannis Harder 47639f8a98
Merge pull request #5388 from jix/bufnorm-followup 
Refactor and fixes to incremental bufNormalize + related changes
 2025-09-29 15:15:29 +02:00
Jannis Harder 6a7372626a
Merge pull request #5389 from jix/sva_continue 
verific: New `-sva-continue-on-error` import option
 2025-09-29 15:07:54 +02:00
Emil J 87c1a868d3
Merge pull request #5384 from rocallahan/simplify-opt-merge-logic 
Move `OptMerge` cell filtering logic to happen while building the cell vector
 2025-09-29 15:03:01 +02:00
Martin Povišer a9318db2fa opt_hier: Adjust messages 2025-09-29 12:27:27 +02:00
Martin Povišer ffe2f7a16d opt_hier: Fix two optimizations conflicting 
Fix a conflict between the following two:

 * propagation of tied-together inputs in
 * propagation of unused inputs out
 2025-09-29 12:27:27 +02:00
Jannis Harder cbc1055517 opt_clean: Fix debug output when cleaning up bufnorm cells 2025-09-29 08:21:28 +02:00
Jannis Harder 9396e5e5fe portarcs: Ignore all bufnorm helper cells 
The `portarcs` pass was already ignoring `$buf` cells when loading
timing data, but now bufnorm will also emit `$input_port` and `$connect`
helper cells, which need to be ignored as well.
 2025-09-29 08:21:28 +02:00
Jannis Harder ce5d04a42f hierarchy: Suggest more specific command to skip unsupported SVA 2025-09-26 18:41:26 +02:00
KrystalDelusion 7ebd972165
Merge pull request #5277 from YosysHQ/krys/fix_4983_alt 
autoname: Avoid integer overflow
 2025-09-26 14:11:20 +12:00
Krystine Sherwin fef6bdae6c
autoname.cc: Return number of renames 
Was previously the number of proposed renames, but since renames can be skipped this causes the final count to differ from the number of actually renamed objects.
Check counts in `tests/various/autoname.ys`.
 2025-09-26 11:05:50 +12:00
Emil J 8c8d18f2d8
Merge pull request #5392 from rocallahan/opt-merge-cleanup 
Some small readability improvements to `OptMergeWorker`
 2025-09-25 12:15:33 +02:00
Martin Povišer 29e0144ebc
Merge pull request #5381 from povik/abc9-multilib 
Support multiple lib files in abc9_exe
 2025-09-25 09:45:09 +02:00
Robert O'Callahan 4d209c187d Switch OptMergeWorker cell type switching to use IdString::in() 2025-09-25 03:06:58 +00:00
Robert O'Callahan 1c73011e7e Swap SigSpecs using std::swap with moves 2025-09-25 03:04:17 +00:00
Jannis Harder 83dd99efb7 verific: New `-sva-continue-on-error` import option 
This option allows you to process a design that includes unsupported
SVA. Unsupported SVA gets imported as formal cells using 'x inputs and
with the `unsupported_sva` attribute set. This allows you to get a
complete list of defined properties or to check only a supported subset
of properties. To ensure no properties are unintentionally skipped for
actual verification, even in cases where `-sva-continue-on-error` is
used by default to read and inspect a design, `hierarchy -simcheck` and
`hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva`
property cells remain in the design.
 2025-09-24 18:58:54 +02:00
Jannis Harder 71882debe7 simplemap: Remove leftover debug output 2025-09-24 13:20:27 +02:00
Jannis Harder 904d49c6d8 abc9_ops: Remove temporary debug log message 
I missed this when adding the -replace_zbufs option.
 2025-09-24 13:20:27 +02:00
Emil Jiří Tywoniak 4508676e67 libcache: support liberty filename globbing 2025-09-24 11:41:51 +02:00
Emil Jiří Tywoniak 856a387aad dfflibmap: support liberty filename globbing 2025-09-24 11:41:51 +02:00
Emil Jiří Tywoniak a28c0c632b clockgate: support liberty filename globbing 2025-09-24 11:41:51 +02:00
Jannis Harder 7a69dbb63d
Merge pull request #5372 from rocallahan/abc-done 
Make ABC_DONE tracking more robust
 2025-09-24 08:40:26 +02:00
Robert O'Callahan e9aacd8a05 Move `OptMerge` cell filtering logic to happen while building the cell vector. 
This code is quite confusing because there are two "is the cell known" filters
applied, one while building the cell vector and one after building the cell
vector, and they're subtly different. I'm preserving the actual behaviour here
but it looks like there is, or was, a bug here.
 2025-09-23 23:26:47 +00:00
Emil J 5f6819fd76
Merge pull request #5361 from YosysHQ/emil/simplemap-transfer-src 
simplemap: fix src attribute transfer
 2025-09-23 20:40:57 +02:00
Martin Povišer 3f4b6dc5d3 Support multiple lib files in abc9_exe 2025-09-23 20:34:08 +02:00
KrystalDelusion d4071b63f7
Merge pull request #5268 from YosysHQ/krys/cutpoint_inout 
Track wire drivers in cutpoint
 2025-09-24 04:14:19 +12:00
Robert O'Callahan 1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Jannis Harder 13a2481da7
Merge pull request #5365 from rocallahan/deterministic-abc 
Extract ABC results in the order of `assigned_cells`
 2025-09-22 23:21:11 +02:00
Emil J a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 
write_rtlil: don't sort
 2025-09-22 11:14:39 +02:00
Robert O'Callahan 7f6fae1f66 Extract ABC results in the order of `assigned_cells`. 
Currently the order of extraction can vary based on which ABC runs finish first. That's
nondeterministic, therefore bad. Instead, force the processing to happen in the same order
as `assigned_cells`, i.e. the same order we use when not using parallelism. This should
make everything deterministic.

Note that we still allow ABC runs to complete out of order. Out-of-order results are
just not extracted until all the previous runs have completed and their results
extracted.
 2025-09-22 05:07:03 +00:00
Robert O'Callahan 4fc782ef2b Make ABC_DONE detection more robust. 
1) Change token from ABC_DONE to YOSYS_ABC_DONE to be a bit more robust against false matches.
2) Emit the token from the sourced script so that we don't have to worry about it showing up in the echoing
of the command as it executes. It will only appear in ABC stdout when it executes, i.e. when
our script has completed.
3) `set abcout` doesn't actually switch ABC to line buffering on stdout, since HAVE_SETVBUF is not actually
set in ABC builds in general. So stop using that. ABC does the necessary flushing when
`source` has finished.
 2025-09-22 05:01:51 +00:00
Robert O'Callahan 2de641d051 Don't redirect spawned ABCs' stderr to our pipe. 
popen() doesn't do this and we should emulate the behavior of popen() as much as possible.
 2025-09-22 05:01:51 +00:00
Robert O'Callahan 4fe21dd652 Reduce hashops verbiage in OptMergePass 2025-09-19 03:31:46 +00:00
Emil J. Tywoniak 96f87aa2d4 simplemap: fix src attribute transfer 2025-09-18 12:59:12 +02:00
Jannis Harder 4f239b536b abc_new: Hide buffered 'z drivers from read/write_xaiger2 
With the updated bufnorm code, buffered 'z drivers are used as anchor
points for undirected connections. These are currently not supported by
read/write_xaiger2, so we temporarily replace those by roughly
equivalent $tribuf cells which will be handled as blackboxes that
properly roundtrip through the xaiger2 front and backend.
 2025-09-17 13:56:46 +02:00
Jannis Harder 5f79a6e868 Clean up $buf with 'z inputs, $input_port and $connect cells 
This ensures that entering and leaving bufnorm followed by `opt_clean`
is equivalent to just running `opt_clean`.

Also make sure that 'z-$buf cells get techmapped in a compatible way.
 2025-09-17 13:56:46 +02:00
Emil J 73e47ac3fe
Merge pull request #5357 from rocallahan/builtin-ff 
Instead of using `builtin_ff_cell_types()` directly, go through a method `Cell::is_builtin_ff()`
 2025-09-17 11:37:16 +02:00
Robert O'Callahan d24488d3a5 Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff() 2025-09-17 03:24:19 +00:00
Robert O'Callahan a7c46f7b4a Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
Robert O'Callahan d1fd6de6da Remove .c_str() calls from parameters to log_header() 2025-09-16 23:00:42 +00:00
Robert O'Callahan 5ac6858f26 Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
Jannis Harder b95549b469
Merge pull request #5348 from rocallahan/remove-string_buf 
Remove `string_buf` by making `log_signal()` and `log_const()` return `std::string`
 2025-09-16 20:20:56 +02:00
Emil J. Tywoniak 73747f6928 read_verilog: add -relativeshare for synthesis reproducibility testing 2025-09-16 15:47:35 +02:00
Emil J. Tywoniak 68ad52c6ae bugpoint: don't sort 2025-09-16 15:39:13 +02:00
Emil J. Tywoniak e11ea42af0 raise_error: whitespace 2025-09-16 15:39:13 +02:00
Robert O'Callahan 7f247fb125 Update passes/hierarchy to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan 159ca3ba56 Update passes/tests to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan 8cc86b2643 Update passes/techmap to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan d1642bf510 Update passes/sat to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan 2d5ce8c363 Update passes/proc to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan 5600eb2e5b Update passes/opt to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan 23f196a3b8 Update passes/memory to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan e1d0c010ef Update passes/fsm to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan 1b589b065d Update passes/cmds to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan 8492c49f6c Remove `string_buf` by making `log_signal()` and `log_const()` return `std::string` 
We only have to fix one caller in-tree so this probably has very low impact on out-of-tree plugins.

Resolves #5215
 2025-09-16 03:06:17 +00:00
Robert O'Callahan ae0ca7578a Use a pool of ABC processes. 
Doing ABC runs in parallel can actually make things slower when every ABC run requires
spawning an ABC subprocess --- especially when using popen(), which on glibc does not
use vfork(). What seems to happen is that constant fork()ing keeps making the main
process data pages copy-on-write, so the main process code that is setting up each ABC
call takes a lot of minor page-faults, slowing it down.

The solution is pretty straightforward although a little tricky to implement.
We just reuse ABC subprocesses. Instead of passing the ABC script name on the command
line, we spawn an ABC REPL and pipe a command into it to source the script. When that's
done we echo an `ABC_DONE` token instead of exiting. Yosys then puts the ABC process
onto a stack which we can pull from the next time we do an ABC run.

For one of our large designs, this is an additional 5x speedup of the primary AbcPass.
It does 5155 ABC runs, all very small; runtime of the AbcPass goes from 760s to 149s
(not very scientific benchmarking but the effect size is large).
 2025-09-15 17:22:15 +02:00
Robert O'Callahan 27462da208 Run ABCs in parallel. 
Large circuits can run hundreds or thousands of ABCs in a single AbcPass.
For some circuits, some of those ABC runs can run for hundreds of seconds.
Running ABCs in parallel with each other and in parallel with main-thread
processing (reading and writing BLIF files, copying ABC BLIF output into
the design) can give large speedups.
 2025-09-15 17:18:42 +02:00
Robert O'Callahan 38f8165c80 Remove direct RTLIL access from gate_t 2025-09-15 17:10:20 +02:00
Robert O'Callahan 222f457a04 Only write out stdcells/lutcosts once for all ABC runs 2025-09-15 17:10:07 +02:00
Robert O'Callahan 13b3418a7f Split `abc_module()` into `prepare_module()` and `run_abc()` 
`prepare_module()` will have to run on the main thread.
 2025-09-15 17:01:25 +02:00
Claire Xen a2fc7e4dd7
Merge pull request #4252 from zapta/master 
Added to the Show command a -wireshape <graphviz-shape> flag.
 2025-09-15 15:40:40 +02:00
Jannis Harder dd9627ed05
Merge pull request #5336 from rocallahan/remove-log-cstr 
Remove `.c_str()` calls from `log()`/`log_error()`
 2025-09-12 14:09:48 +02:00
Krystine Sherwin f102b25914 Reapply "Merge pull request #5301 from KrystalDelusion/krys/re_5280" 
This reverts commit 88eb83a0c3.
 2025-09-12 10:41:01 +02:00